Algorithm-Centric Design of Reliable and Efficient Deep Learning Processing Systems- [electronic resource]
Algorithm-Centric Design of Reliable and Efficient Deep Learning Processing Systems- [electronic resource]
- 자료유형
- 학위논문파일 국외
- 최종처리일시
- 20240214100428
- ISBN
- 9798379759209
- DDC
- 004
- 저자명
- Ozen, Elbruz.
- 서명/저자
- Algorithm-Centric Design of Reliable and Efficient Deep Learning Processing Systems - [electronic resource]
- 발행사항
- [S.l.]: : University of California, San Diego., 2023
- 발행사항
- Ann Arbor : : ProQuest Dissertations & Theses,, 2023
- 형태사항
- 1 online resource(303 p.)
- 주기사항
- Source: Dissertations Abstracts International, Volume: 84-12, Section: A.
- 주기사항
- Advisor: Orailoglu, Alex.
- 학위논문주기
- Thesis (Ph.D.)--University of California, San Diego, 2023.
- 사용제한주기
- This item must not be sold to any third party vendors.
- 초록/해제
- 요약Artificial intelligence techniques driven by deep learning have experienced significant advancements in the past decade. The usage of deep learning methods has increased dramatically in practical application domains such as autonomous driving, healthcare, and robotics, where the utmost hardware resource efficiency, as well as strict hardware safety and reliability requirements, are often imposed. The increasing computational cost of deep learning models has been traditionally tackled through model compression and domain-specific accelerator design. As the cost of conventional fault tolerance methods is often prohibitive in consumer electronics, the question of functional safety and reliability for deep learning hardware is still in its infancy. This dissertation outlines a novel approach to deliver dramatic boosts in hardware safety, reliability, and resource efficiency through a synergistic co-design paradigm. We first observe and make use of the unique algorithmic characteristics of deep neural networks, including plasticity in the design process, resiliency to small numerical perturbations, and their inherent redundancy, as well as the unique micro-architectural properties of deep learning accelerators such as regularity. The advocated approach is accomplished by reshaping deep neural networks, enhancing deep neural network accelerators strategically, prioritizing the overall functional correctness, and minimizing the associated costs through the statistical nature of deep neural networks. To illustrate, our analysis demonstrates that deep neural networks equipped with the proposed techniques can maintain accuracy gracefully, even at extreme rates of hardware errors. As a result, the described methodology can embed strong safety and reliability characteristics in mission-critical deep learning applications at a negligible cost. The proposed approach further offers a promising avenue for handling the micro-architectural challenges of deep neural network accelerators and boosting resource efficiency through the synergistic co-design of deep neural networks and hardware micro-architectures.
- 일반주제명
- Computer science.
- 일반주제명
- Computer engineering.
- 일반주제명
- Information science.
- 키워드
- Deep learning
- 키워드
- Hardware
- 키워드
- Hardware errors
- 기타저자
- University of California, San Diego Computer Science and Engineering
- 기본자료저록
- Dissertations Abstracts International. 84-12A.
- 기본자료저록
- Dissertation Abstract International
- 전자적 위치 및 접속
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