Design Methodologies and Automated Generation of Ultra High Speed Wireline SerDes Transmitters- [electronic resource]
Design Methodologies and Automated Generation of Ultra High Speed Wireline SerDes Transmitters- [electronic resource]
- 자료유형
- 학위논문파일 국외
- 최종처리일시
- 20240214101652
- ISBN
- 9798380366946
- DDC
- 621.3
- 저자명
- Biswas, Ayan.
- 서명/저자
- Design Methodologies and Automated Generation of Ultra High Speed Wireline SerDes Transmitters - [electronic resource]
- 발행사항
- [S.l.]: : University of California, Berkeley., 2023
- 발행사항
- Ann Arbor : : ProQuest Dissertations & Theses,, 2023
- 형태사항
- 1 online resource(77 p.)
- 주기사항
- Source: Dissertations Abstracts International, Volume: 85-03, Section: B.
- 주기사항
- Advisor: Stojanovic, Vladimir;Alon, Elad.
- 학위논문주기
- Thesis (Ph.D.)--University of California, Berkeley, 2023.
- 사용제한주기
- This item must not be sold to any third party vendors.
- 초록/해제
- 요약With the ever increasing bandwidth demand in high performance computing, network and communications, machine learning applications, etc, wireline data transfer between multiple chips on the same package has been doubling in per-lane data rate every 3-4 years. The challenging design complexity of the analog and mixed signal front-end circuits necessitates the use of automated process portable layout generators and closed loop design scripts to reduce the turn-around time from circuit design to tape-outs in advanced FinFET technology nodes.To that end, this thesis introduces new feature improvements in the Berkeley Analog Generator (BAG) 3++, which is an open source framework for automating process portable circuit generation and encoding closed loop design methodologies. Then the thesis presents the design of a 160 Gbps NRZ transmitter (TX) targeting low loss (∼3dB) ultra short reach channels for die-to-die data transfer, with 2 tap FFE for pre-equalization. Some major challenges in this effort are the design of a high speed 8:1 mux stage using inductor-based peaking topologies, and a novel method of creating the 1 UI delayed data stream for the FFE precursor using the available octature clock phases. The TX is taped out in Intel16 process as a part of a complete 160 Gbps NRZ transceiver design, and tested in loopback mode by serially transmitting data to the receiver over a 8.5 mm differential channel on package.
- 일반주제명
- Electrical engineering.
- 일반주제명
- Engineering.
- 일반주제명
- Computer engineering.
- 키워드
- Machine learning
- 키워드
- Closed loop
- 기타저자
- University of California, Berkeley Electrical Engineering & Computer Sciences
- 기본자료저록
- Dissertations Abstracts International. 85-03B.
- 기본자료저록
- Dissertation Abstract International
- 전자적 위치 및 접속
- 로그인 후 원문을 볼 수 있습니다.