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Co-Design of Algorithms, Hardware, and Scheduling for Deep Learning Applications- [electronic resource]
Co-Design of Algorithms, Hardware, and Scheduling for Deep Learning Applications- [electronic resource]
상세정보
- 자료유형
- 학위논문파일 국외
- 최종처리일시
- 20240214100319
- ISBN
- 9798380620130
- DDC
- 004
- 저자명
- Huang, Qijing.
- 서명/저자
- Co-Design of Algorithms, Hardware, and Scheduling for Deep Learning Applications - [electronic resource]
- 발행사항
- [S.l.]: : University of California, Berkeley., 2021
- 발행사항
- Ann Arbor : ProQuest Dissertations & Theses, 2021
- 형태사항
- 1 online resource(160 p.)
- 주기사항
- Source: Dissertations Abstracts International, Volume: 85-04, Section: B.
- 주기사항
- Advisor: Wawrzynek, John.
- 학위논문주기
- Thesis (Ph.D.)--University of California, Berkeley, 2021.
- 사용제한주기
- This item must not be sold to any third party vendors.
- 초록/해제
- 요약For decades, ever-increasing computing power has been a driving force behind many technology revolutions, including the recent advances in artificial intelligence. However, due to the slowing of integrated circuit process scaling, for system architects to continue to satisfy the ever-growing compute appetite of today's applications, they must now resort to employing heterogeneous systems with specialized accelerators.Building these accelerator systems, though, is extremely expensive and time-consuming. First, the development cycle for hardware is notoriously long, making it difficult to keep up with the rapid progress in algorithms. Meanwhile, existing compilers are incapable of navigating the intractable mapping space exposed by the novel accelerator architectures. Lastly, algorithms are often designed without hardware efficiency as a key metric, and therefore, pose extra challenges in designing efficient hardware.This thesis tackles the significant challenges in jointly designing and optimizing algorithms, scheduling, and hardware designs for acceleration. We aim to advance the state-of-the-art through a three-pronged approach: the development of methodologies and tools that automatically generate accelerator systems from high-level abstractions, shortening the hardware development cycle; the adaptation of machine learning and other optimization techniques to improve accelerator design and compilation flows; and the co-design of algorithms and accelerators to exploit more optimization opportunities.The target application domain of this thesis is deep learning which has achieved unprecedented success in a wide range of tasks such as computer vision, neural language processing, etc. As intelligent devices prevail, deep learning is foreseeably becoming a major computation demand in our everyday life. Therefore, by performing end-to-end system optimization with hardware acceleration, the dissertation aims to unleash the ubiquitous adoption of cutting-edge deep learning algorithms to transform various aspects of life.
- 일반주제명
- Computer science.
- 일반주제명
- Computer engineering.
- 일반주제명
- Electrical engineering.
- 키워드
- Accelerators
- 키워드
- Co-design
- 키워드
- Deep learning
- 키워드
- Machine learning
- 기타저자
- University of California, Berkeley Computer Science
- 기본자료저록
- Dissertations Abstracts International. 85-04B.
- 기본자료저록
- Dissertation Abstract International
- 전자적 위치 및 접속
- 로그인 후 원문을 볼 수 있습니다.
MARC
008240612s2021 us |||||||||||||||c||eng d■001000016931869
■00520240214100319
■006m o d
■007cr#unu||||||||
■020 ▼a9798380620130
■035 ▼a(MiAaPQ)AAI28717991
■040 ▼aMiAaPQ▼cMiAaPQ
■0820 ▼a004
■1001 ▼aHuang, Qijing.
■24510▼aCo-Design of Algorithms, Hardware, and Scheduling for Deep Learning Applications▼h[electronic resource]
■260 ▼a[S.l.]:▼bUniversity of California, Berkeley. ▼c2021
■260 1▼aAnn Arbor▼bProQuest Dissertations & Theses▼c2021
■300 ▼a1 online resource(160 p.)
■500 ▼aSource: Dissertations Abstracts International, Volume: 85-04, Section: B.
■500 ▼aAdvisor: Wawrzynek, John.
■5021 ▼aThesis (Ph.D.)--University of California, Berkeley, 2021.
■506 ▼aThis item must not be sold to any third party vendors.
■520 ▼aFor decades, ever-increasing computing power has been a driving force behind many technology revolutions, including the recent advances in artificial intelligence. However, due to the slowing of integrated circuit process scaling, for system architects to continue to satisfy the ever-growing compute appetite of today's applications, they must now resort to employing heterogeneous systems with specialized accelerators.Building these accelerator systems, though, is extremely expensive and time-consuming. First, the development cycle for hardware is notoriously long, making it difficult to keep up with the rapid progress in algorithms. Meanwhile, existing compilers are incapable of navigating the intractable mapping space exposed by the novel accelerator architectures. Lastly, algorithms are often designed without hardware efficiency as a key metric, and therefore, pose extra challenges in designing efficient hardware.This thesis tackles the significant challenges in jointly designing and optimizing algorithms, scheduling, and hardware designs for acceleration. We aim to advance the state-of-the-art through a three-pronged approach: the development of methodologies and tools that automatically generate accelerator systems from high-level abstractions, shortening the hardware development cycle; the adaptation of machine learning and other optimization techniques to improve accelerator design and compilation flows; and the co-design of algorithms and accelerators to exploit more optimization opportunities.The target application domain of this thesis is deep learning which has achieved unprecedented success in a wide range of tasks such as computer vision, neural language processing, etc. As intelligent devices prevail, deep learning is foreseeably becoming a major computation demand in our everyday life. Therefore, by performing end-to-end system optimization with hardware acceleration, the dissertation aims to unleash the ubiquitous adoption of cutting-edge deep learning algorithms to transform various aspects of life.
■590 ▼aSchool code: 0028.
■650 4▼aComputer science.
■650 4▼aComputer engineering.
■650 4▼aElectrical engineering.
■653 ▼aAccelerators
■653 ▼aCo-design
■653 ▼aDeep learning
■653 ▼aMachine learning
■653 ▼aHardware acceleration
■690 ▼a0984
■690 ▼a0464
■690 ▼a0544
■690 ▼a0800
■71020▼aUniversity of California, Berkeley▼bComputer Science.
■7730 ▼tDissertations Abstracts International▼g85-04B.
■773 ▼tDissertation Abstract International
■790 ▼a0028
■791 ▼aPh.D.
■792 ▼a2021
■793 ▼aEnglish
■85640▼uhttp://www.riss.kr/pdu/ddodLink.do?id=T16931869▼nKERIS▼z이 자료의 원문은 한국교육학술정보원에서 제공합니다.
■980 ▼a202402▼f2024
