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Design Technology Co-optimization of Energy-Efficient Digital Logic Using Carbon Nanotubes
Design Technology Co-optimization of Energy-Efficient Digital Logic Using Carbon Nanotubes
상세정보
- 자료유형
- 학위논문 서양
- 최종처리일시
- 20250211151404
- ISBN
- 9798382232478
- DDC
- 620.11
- 저자명
- Carlo Gilardi.
- 서명/저자
- Design Technology Co-optimization of Energy-Efficient Digital Logic Using Carbon Nanotubes
- 발행사항
- [Sl] : Stanford University, 2024
- 발행사항
- Ann Arbor : ProQuest Dissertations & Theses, 2024
- 형태사항
- 136 p
- 주기사항
- Source: Dissertations Abstracts International, Volume: 85-11, Section: B.
- 주기사항
- Advisor: Subhasish Mitra.
- 학위논문주기
- Thesis (Ph.D.)--Stanford University, 2024.
- 초록/해제
- 요약Carbon Nanotube field-effect transistors (FETs) are promising candidates for high-speed and low- energy digital logic, Carbon Nanotube FETs have been integrated within multiple industrial fabrication facilities at mature technology nodes (e.g., 90/130nm on 200mm silicon wafers). However, understanding Carbon Nanotube FET energy and delay benefits at extremely scaled nodes (e.g., beyond 2nm) is difficult due to several reasons:1. Carbon Nanotube FETs have distinct characteristics material properties and fabrication techniques versus silicon FETs, that directly impact digital logic energy and delay.2. Carbon Nanotube FET energy efficiency analysis must include Carbon Nanotube FET mini- mum leakage current.3. Carbon Nanotube FET digital logic energy and delay exhibit numerous trade-offs, far beyond those for silicon FETs.I address these challenges through new physics-based models using physically meaningful parameters, new Carbon Nanotube FET doping and layout design techniques, and extensive Design Technology Co-Optimization.To illustrate new physics-based models, I present the extended scale length theory. It captures the differences between Carbon Nanotube FET and silicon FET electrostatics that are crucial for energy and delay estimation. The extended scale length theory is also used as a mathematical framework for the development of a leakage model that includes the leakage mechanisms relevant for Carbon Nanotube FETs at extremely scaled nodes (e.g., inelastic band-to-band tunneling). The leakage model is used to quantify Carbon Nanotube FET minimum leakage current within 3x vs. experimentally calibrated Non-Equilibrium Green's Function (NEGF) solvers. In contrast, prior models that do not include all the relevant leakage mechanisms can underestimate Carbon Nanotube FET minimum leakage current by a factor of 105.Understanding Carbon Nanotube FET digital logic energy and delay trade-offs requires extensive Design Technology Co-Optimization simulations across many design and technology parameters. My new physics-based models enable fast Design Technology Co-Optimization: over 350,000 simulations in a few days vs. several months using existing Technology CAD simulators. Such extensive Design Technology Co-Optimization helps derive Carbon Nanotube FET design and technology parameters with up to 7x projected Energy-Delay Product (EDP) benefits vs. silicon FETs at the 2nm technology node. These Design Technology Co-Optimization simulations also include a new Carbon Nanotube FET extension doping technique based on the concept of a barrier booster.A new logic layout technique called Omni 3D exploits Carbon Nanotube FET low-temperature fabrication to further enable up to 1.9x additional projected EDP benefits. Several of my thesis contributions extend beyond Carbon Nanotube FETs, e.g., to FETs based on two-dimensional materials.
- 일반주제명
- Materials science
- 일반주제명
- Energy
- 일반주제명
- Electrical engineering
- 기타저자
- Stanford University.
- 기본자료저록
- Dissertations Abstracts International. 85-11B.
- 전자적 위치 및 접속
- 로그인 후 원문을 볼 수 있습니다.
MARC
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■020 ▼a9798382232478
■035 ▼a(MiAaPQ)AAI31255797
■035 ▼a(MiAaPQ)jq719cs3351
■040 ▼aMiAaPQ▼cMiAaPQ
■0820 ▼a620.11
■1001 ▼aCarlo Gilardi.
■24510▼aDesign Technology Co-optimization of Energy-Efficient Digital Logic Using Carbon Nanotubes
■260 ▼a[Sl]▼bStanford University▼c2024
■260 1▼aAnn Arbor▼bProQuest Dissertations & Theses▼c2024
■300 ▼a136 p
■500 ▼aSource: Dissertations Abstracts International, Volume: 85-11, Section: B.
■500 ▼aAdvisor: Subhasish Mitra.
■5021 ▼aThesis (Ph.D.)--Stanford University, 2024.
■520 ▼aCarbon Nanotube field-effect transistors (FETs) are promising candidates for high-speed and low- energy digital logic, Carbon Nanotube FETs have been integrated within multiple industrial fabrication facilities at mature technology nodes (e.g., 90/130nm on 200mm silicon wafers). However, understanding Carbon Nanotube FET energy and delay benefits at extremely scaled nodes (e.g., beyond 2nm) is difficult due to several reasons:1. Carbon Nanotube FETs have distinct characteristics material properties and fabrication techniques versus silicon FETs, that directly impact digital logic energy and delay.2. Carbon Nanotube FET energy efficiency analysis must include Carbon Nanotube FET mini- mum leakage current.3. Carbon Nanotube FET digital logic energy and delay exhibit numerous trade-offs, far beyond those for silicon FETs.I address these challenges through new physics-based models using physically meaningful parameters, new Carbon Nanotube FET doping and layout design techniques, and extensive Design Technology Co-Optimization.To illustrate new physics-based models, I present the extended scale length theory. It captures the differences between Carbon Nanotube FET and silicon FET electrostatics that are crucial for energy and delay estimation. The extended scale length theory is also used as a mathematical framework for the development of a leakage model that includes the leakage mechanisms relevant for Carbon Nanotube FETs at extremely scaled nodes (e.g., inelastic band-to-band tunneling). The leakage model is used to quantify Carbon Nanotube FET minimum leakage current within 3x vs. experimentally calibrated Non-Equilibrium Green's Function (NEGF) solvers. In contrast, prior models that do not include all the relevant leakage mechanisms can underestimate Carbon Nanotube FET minimum leakage current by a factor of 105.Understanding Carbon Nanotube FET digital logic energy and delay trade-offs requires extensive Design Technology Co-Optimization simulations across many design and technology parameters. My new physics-based models enable fast Design Technology Co-Optimization: over 350,000 simulations in a few days vs. several months using existing Technology CAD simulators. Such extensive Design Technology Co-Optimization helps derive Carbon Nanotube FET design and technology parameters with up to 7x projected Energy-Delay Product (EDP) benefits vs. silicon FETs at the 2nm technology node. These Design Technology Co-Optimization simulations also include a new Carbon Nanotube FET extension doping technique based on the concept of a barrier booster.A new logic layout technique called Omni 3D exploits Carbon Nanotube FET low-temperature fabrication to further enable up to 1.9x additional projected EDP benefits. Several of my thesis contributions extend beyond Carbon Nanotube FETs, e.g., to FETs based on two-dimensional materials.
■590 ▼aSchool code: 0212.
■650 4▼aMaterials science
■650 4▼aEnergy
■650 4▼aElectrical engineering
■653 ▼aCarbon Nanotube field-effect transistors
■653 ▼aFabrication techniques
■690 ▼a0544
■690 ▼a0794
■690 ▼a0791
■71020▼aStanford University.
■7730 ▼tDissertations Abstracts International▼g85-11B.
■790 ▼a0212
■791 ▼aPh.D.
■792 ▼a2024
■793 ▼aEnglish
■85640▼uhttp://www.riss.kr/pdu/ddodLink.do?id=T17161493▼nKERIS▼z이 자료의 원문은 한국교육학술정보원에서 제공합니다.


