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PLL Design for FMCW Radar Systems
PLL Design for FMCW Radar Systems
상세정보
- 자료유형
- 학위논문 서양
- 최종처리일시
- 20250211151457
- ISBN
- 9798384447689
- DDC
- 621.3
- 저자명
- Liu, Benyuanyi.
- 서명/저자
- PLL Design for FMCW Radar Systems
- 발행사항
- [Sl] : University of California, Berkeley, 2024
- 발행사항
- Ann Arbor : ProQuest Dissertations & Theses, 2024
- 형태사항
- 121 p
- 주기사항
- Source: Dissertations Abstracts International, Volume: 86-03, Section: B.
- 주기사항
- Advisor: Niknejad, Ali M.
- 학위논문주기
- Thesis (Ph.D.)--University of California, Berkeley, 2024.
- 초록/해제
- 요약In this thesis, the PLL design for FMCW radar systems is illustrated. The FMCW radar imposes requirements on the PLL-based chirp generator in several aspects. Both the phase noise and the bandwidth of the PLL influence the measurement accuracy and resolution of the radar. The phase noise should be minimized, given a certain power consumption, and the bandwidth needs to be matched with the FMCW chirp slope to achieve better linearity.For system-level design, unlike PLLs for other applications, the output of the chirp generator PLL is always changing. In many applications, such as precision measurement, the output never truly settles at each step. This necessitates careful modeling of the loop dynamics. In this thesis, conventional PLL phase noise and settling time models are presented and adapted for the chirp generator. However, these models are insufficient for optimizing the design. Therefore, a more accurate time-domain model for calculating the chirp is proposed. This model aids in designing the PLL bandwidth, calculating the acceptable chirp slope for a given PLL, and computing the dynamic phase noise. To the best of our knowledge, this is the first relatively accurate model for the entire chirp generation process.For the design of circuit blocks, the frequency division modules, which include a dual-modulus divider and a Delta-Sigma Modulator, are presented. For the high-frequency circuit, an analytical model and a corresponding design methodology are proposed. The PLL has been taped-out, and measurements will be conducted to confirm the performance and design methodology.
- 일반주제명
- Electrical engineering
- 일반주제명
- Computer science
- 키워드
- Chirp generator
- 키워드
- Loop dynamics
- 기타저자
- University of California, Berkeley Electrical Engineering & Computer Sciences
- 기본자료저록
- Dissertations Abstracts International. 86-03B.
- 전자적 위치 및 접속
- 로그인 후 원문을 볼 수 있습니다.
MARC
008250123s2024 us c eng d■001000017161883
■00520250211151457
■006m o d
■007cr#unu||||||||
■020 ▼a9798384447689
■035 ▼a(MiAaPQ)AAI31297307
■040 ▼aMiAaPQ▼cMiAaPQ
■0820 ▼a621.3
■1001 ▼aLiu, Benyuanyi.
■24510▼aPLL Design for FMCW Radar Systems
■260 ▼a[Sl]▼bUniversity of California, Berkeley▼c2024
■260 1▼aAnn Arbor▼bProQuest Dissertations & Theses▼c2024
■300 ▼a121 p
■500 ▼aSource: Dissertations Abstracts International, Volume: 86-03, Section: B.
■500 ▼aAdvisor: Niknejad, Ali M.
■5021 ▼aThesis (Ph.D.)--University of California, Berkeley, 2024.
■520 ▼aIn this thesis, the PLL design for FMCW radar systems is illustrated. The FMCW radar imposes requirements on the PLL-based chirp generator in several aspects. Both the phase noise and the bandwidth of the PLL influence the measurement accuracy and resolution of the radar. The phase noise should be minimized, given a certain power consumption, and the bandwidth needs to be matched with the FMCW chirp slope to achieve better linearity.For system-level design, unlike PLLs for other applications, the output of the chirp generator PLL is always changing. In many applications, such as precision measurement, the output never truly settles at each step. This necessitates careful modeling of the loop dynamics. In this thesis, conventional PLL phase noise and settling time models are presented and adapted for the chirp generator. However, these models are insufficient for optimizing the design. Therefore, a more accurate time-domain model for calculating the chirp is proposed. This model aids in designing the PLL bandwidth, calculating the acceptable chirp slope for a given PLL, and computing the dynamic phase noise. To the best of our knowledge, this is the first relatively accurate model for the entire chirp generation process.For the design of circuit blocks, the frequency division modules, which include a dual-modulus divider and a Delta-Sigma Modulator, are presented. For the high-frequency circuit, an analytical model and a corresponding design methodology are proposed. The PLL has been taped-out, and measurements will be conducted to confirm the performance and design methodology.
■590 ▼aSchool code: 0028.
■650 4▼aElectrical engineering
■650 4▼aComputer science
■653 ▼aChirp generator
■653 ▼aDesign methodology
■653 ▼aPower consumption
■653 ▼aLoop dynamics
■690 ▼a0544
■690 ▼a0984
■71020▼aUniversity of California, Berkeley▼bElectrical Engineering & Computer Sciences.
■7730 ▼tDissertations Abstracts International▼g86-03B.
■790 ▼a0028
■791 ▼aPh.D.
■792 ▼a2024
■793 ▼aEnglish
■85640▼uhttp://www.riss.kr/pdu/ddodLink.do?id=T17161883▼nKERIS▼z이 자료의 원문은 한국교육학술정보원에서 제공합니다.
