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The Design and Verification of Compilers for Domain-Specific Reconfigurable Accelerators
The Design and Verification of Compilers for Domain-Specific Reconfigurable Accelerators
상세정보
- 자료유형
- 학위논문 서양
- 최종처리일시
- 20250211153058
- ISBN
- 9798346390473
- DDC
- 629.4
- 서명/저자
- The Design and Verification of Compilers for Domain-Specific Reconfigurable Accelerators
- 발행사항
- [Sl] : Stanford University, 2024
- 발행사항
- Ann Arbor : ProQuest Dissertations & Theses, 2024
- 형태사항
- 126 p
- 주기사항
- Source: Dissertations Abstracts International, Volume: 86-05, Section: B.
- 주기사항
- Advisor: Raina, Priyanka.
- 학위논문주기
- Thesis (Ph.D.)--Stanford University, 2024.
- 초록/해제
- 요약The rapid growth of artificial intelligence (AI) has fueled the need for high-performance and energy-efficient hardware accelerators. However, because AI models evolve very rapidly, these accelerators need to be programmable to avoid becoming obsolete. Coarse-grained reconfigurable arrays (CGRAs) are a class of accelerators that achieve a balance between programmability and efficiency. Unlike field-programmable gate arrays (FPGAs), CGRAs leverage specialized arithmetic units operating at a coarser granularity, offering superior performance and energy efficiency, and unlike application-specific integrated circuits (ASICs), CGRAs offer sufficient programmability to accelerate larger domains of applications and accommodate evolving applications.However, designing a CGRA with the appropriate level of specialization to accelerate a class of applications requires deep knowledge of the applications and significant design effort on both the hardware and the compiler. Furthermore, design choices have a large impact on the power, performance, and area of the resulting accelerator. Additionally, existing CGRA application compilers are often slow, produce applications that cannot run at high clock frequencies, or only target expensive architectures. Finally, while some software compilers and high-level synthesis tools provide formal proofs of correctness using translation validation, CGRA compilers do not have this infrastructure.In this dissertation, I address each of these challenges. I first present APEX, an automated design space exploration tool for CGRA processing elements. APEX utilizes graph analysis and frequent subgraph mining techniques to automatically specialize CGRA architectures to an application domain, achieving 39% less area and 59% less energy compared to a general-purpose CGRA. Next, I describe Cascade, a CGRA application compiler that produces high-performance and energy-efficient application mappings using pipelining techniques developed for CGRAs. Cascade achieves 34x shorter critical paths and 190x lower energy-delay product than existing compilers. Finally, I present a formal translation validation tool for accelerator application compilers that ensures the functionality of an application is unchanged as it gets lowered from specification to hardware, enabling more rigorous verification and faster bug localization than existing solutions.These contributions address major challenges in the design, compilation, and verification of CGRAs, enabling their broader adoption as alternatives to both FPGAs and ASICs for accelerating a wide variety of applications.
- 일반주제명
- Space exploration
- 일반주제명
- Boxes
- 일반주제명
- Aerospace engineering
- 기타저자
- Stanford University.
- 기본자료저록
- Dissertations Abstracts International. 86-05B.
- 전자적 위치 및 접속
- 로그인 후 원문을 볼 수 있습니다.
MARC
008250123s2024 us c eng d■001000017164886
■00520250211153058
■006m o d
■007cr#unu||||||||
■020 ▼a9798346390473
■035 ▼a(MiAaPQ)AAI31652050
■035 ▼a(MiAaPQ)Stanfordkf054zz2443
■040 ▼aMiAaPQ▼cMiAaPQ
■0820 ▼a629.4
■1001 ▼aMelchert, Jackson Henry.
■24510▼aThe Design and Verification of Compilers for Domain-Specific Reconfigurable Accelerators
■260 ▼a[Sl]▼bStanford University▼c2024
■260 1▼aAnn Arbor▼bProQuest Dissertations & Theses▼c2024
■300 ▼a126 p
■500 ▼aSource: Dissertations Abstracts International, Volume: 86-05, Section: B.
■500 ▼aAdvisor: Raina, Priyanka.
■5021 ▼aThesis (Ph.D.)--Stanford University, 2024.
■520 ▼aThe rapid growth of artificial intelligence (AI) has fueled the need for high-performance and energy-efficient hardware accelerators. However, because AI models evolve very rapidly, these accelerators need to be programmable to avoid becoming obsolete. Coarse-grained reconfigurable arrays (CGRAs) are a class of accelerators that achieve a balance between programmability and efficiency. Unlike field-programmable gate arrays (FPGAs), CGRAs leverage specialized arithmetic units operating at a coarser granularity, offering superior performance and energy efficiency, and unlike application-specific integrated circuits (ASICs), CGRAs offer sufficient programmability to accelerate larger domains of applications and accommodate evolving applications.However, designing a CGRA with the appropriate level of specialization to accelerate a class of applications requires deep knowledge of the applications and significant design effort on both the hardware and the compiler. Furthermore, design choices have a large impact on the power, performance, and area of the resulting accelerator. Additionally, existing CGRA application compilers are often slow, produce applications that cannot run at high clock frequencies, or only target expensive architectures. Finally, while some software compilers and high-level synthesis tools provide formal proofs of correctness using translation validation, CGRA compilers do not have this infrastructure.In this dissertation, I address each of these challenges. I first present APEX, an automated design space exploration tool for CGRA processing elements. APEX utilizes graph analysis and frequent subgraph mining techniques to automatically specialize CGRA architectures to an application domain, achieving 39% less area and 59% less energy compared to a general-purpose CGRA. Next, I describe Cascade, a CGRA application compiler that produces high-performance and energy-efficient application mappings using pipelining techniques developed for CGRAs. Cascade achieves 34x shorter critical paths and 190x lower energy-delay product than existing compilers. Finally, I present a formal translation validation tool for accelerator application compilers that ensures the functionality of an application is unchanged as it gets lowered from specification to hardware, enabling more rigorous verification and faster bug localization than existing solutions.These contributions address major challenges in the design, compilation, and verification of CGRAs, enabling their broader adoption as alternatives to both FPGAs and ASICs for accelerating a wide variety of applications.
■590 ▼aSchool code: 0212.
■650 4▼aSpace exploration
■650 4▼aBoxes
■650 4▼aAerospace engineering
■690 ▼a0538
■690 ▼a0800
■71020▼aStanford University.
■7730 ▼tDissertations Abstracts International▼g86-05B.
■790 ▼a0212
■791 ▼aPh.D.
■792 ▼a2024
■793 ▼aEnglish
■85640▼uhttp://www.riss.kr/pdu/ddodLink.do?id=T17164886▼nKERIS▼z이 자료의 원문은 한국교육학술정보원에서 제공합니다.
