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Device Layout Techniques for RF Performance Enhancement on Sige HBTS for Future Generation Bicmos Technology
Device Layout Techniques for RF Performance Enhancement on Sige HBTS for Future Generation Bicmos Technology
상세정보
- 자료유형
- 학위논문 서양
- 최종처리일시
- 20260202105538
- ISBN
- 9798263389802
- DDC
- 620
- 서명/저자
- Device Layout Techniques for RF Performance Enhancement on Sige HBTS for Future Generation Bicmos Technology
- 발행사항
- [Sl] : Georgia Institute of Technology, 2023
- 발행사항
- Ann Arbor : ProQuest Dissertations & Theses, 2023
- 형태사항
- 51 p
- 주기사항
- Source: Dissertations Abstracts International, Volume: 87-05, Section: B.
- 주기사항
- Advisor: Cressler, John D.;Ghalichechian, Nima;Ansari, Azadeh.
- 학위논문주기
- Thesis (Ph.D.)--Georgia Institute of Technology, 2023.
- 초록/해제
- 요약A study of RF performance techniques and their tradeoffs for SiGe heterojunction transistor (HBT) devices was presented. Performance results metrics showed that the τTH can be reduced by up to 37%, with increased fmax (by 17%), increased 1 dB compression point (P1 dB) (by 9%), and higher power-added-efficiency (PAE) (by 1.3%), and increased transducer gain (by 4.7%) using only layout optimization, with only a slight degradation of 4.5% in maximum available gain (MAG), and 8% in fT. The candidate device layouts presented can assist circuit designers in mitigating thermal memory effects at the device level, thereby improving the overall linearity of power amplifiers. This work has been accepted for publication and is available for early access on IEEE Transactions on Electron Devices [1].Similarly, another technique using induced stress to engineer the bandgap and improve performance was presented. The results show that adding more dummy metal layers to the BEOL increases collector current density (JC) and base current density (JB) at most by 25% and 15%, respectively. Similarly, additional dummy metal layers reduce current gain (β) and JB stress degradation by 30% and 100%, respectively. Sentaurus TCAD was used to explain how reduced self-heating contributes more strongly to the Auger generation rate than the stress-induced bandgap modulation, thereby improving reliability. This work has been accepted for publication and presented at the IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium [2].Future work should be focused on how these performance enhancements will be impacted by the RF breakdown due to BEOL dummy layers. In addition, another unexplored aspect of reliability using BEOL dummy metal layers as a performance enhancement technique is operation over a wide range of temperatures and its related physics.
- 일반주제명
- Circuits
- 일반주제명
- Layouts
- 일반주제명
- Design
- 일반주제명
- Heat
- 일반주제명
- Investigations
- 일반주제명
- Transistors
- 일반주제명
- Electrical engineering
- 기본자료저록
- Dissertations Abstracts International. 87-05B.
- 전자적 위치 및 접속
- 로그인 후 원문을 볼 수 있습니다.
MARC
008260126s2023 us c eng d■001000017360512
■00520260202105538
■006m o d
■007cr#unu||||||||
■020 ▼a9798263389802
■035 ▼a(MiAaPQ)AAI32315028
■035 ▼a(MiAaPQ)GeorgiaTech71977
■040 ▼aMiAaPQ▼cMiAaPQ
■0820 ▼a620
■1001 ▼aSepulveda, Nelson E.
■24510▼aDevice Layout Techniques for RF Performance Enhancement on Sige HBTS for Future Generation Bicmos Technology
■260 ▼a[Sl]▼bGeorgia Institute of Technology▼c2023
■260 1▼aAnn Arbor▼bProQuest Dissertations & Theses▼c2023
■300 ▼a51 p
■500 ▼aSource: Dissertations Abstracts International, Volume: 87-05, Section: B.
■500 ▼aAdvisor: Cressler, John D.;Ghalichechian, Nima;Ansari, Azadeh.
■5021 ▼aThesis (Ph.D.)--Georgia Institute of Technology, 2023.
■520 ▼aA study of RF performance techniques and their tradeoffs for SiGe heterojunction transistor (HBT) devices was presented. Performance results metrics showed that the τTH can be reduced by up to 37%, with increased fmax (by 17%), increased 1 dB compression point (P1 dB) (by 9%), and higher power-added-efficiency (PAE) (by 1.3%), and increased transducer gain (by 4.7%) using only layout optimization, with only a slight degradation of 4.5% in maximum available gain (MAG), and 8% in fT. The candidate device layouts presented can assist circuit designers in mitigating thermal memory effects at the device level, thereby improving the overall linearity of power amplifiers. This work has been accepted for publication and is available for early access on IEEE Transactions on Electron Devices [1].Similarly, another technique using induced stress to engineer the bandgap and improve performance was presented. The results show that adding more dummy metal layers to the BEOL increases collector current density (JC) and base current density (JB) at most by 25% and 15%, respectively. Similarly, additional dummy metal layers reduce current gain (β) and JB stress degradation by 30% and 100%, respectively. Sentaurus TCAD was used to explain how reduced self-heating contributes more strongly to the Auger generation rate than the stress-induced bandgap modulation, thereby improving reliability. This work has been accepted for publication and presented at the IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium [2].Future work should be focused on how these performance enhancements will be impacted by the RF breakdown due to BEOL dummy layers. In addition, another unexplored aspect of reliability using BEOL dummy metal layers as a performance enhancement technique is operation over a wide range of temperatures and its related physics.
■590 ▼aSchool code: 0078.
■650 4▼aCircuits
■650 4▼aLayouts
■650 4▼aDesign
■650 4▼aHeat
■650 4▼aInvestigations
■650 4▼aTransistors
■650 4▼aElectrical engineering
■690 ▼a0389
■690 ▼a0544
■71020▼aGeorgia Institute of Technology.
■7730 ▼tDissertations Abstracts International▼g87-05B.
■790 ▼a0078
■791 ▼aPh.D.
■792 ▼a2023
■793 ▼aEnglish
■85640▼uhttp://www.riss.kr/pdu/ddodLink.do?id=T17360512▼nKERIS▼z이 자료의 원문은 한국교육학술정보원에서 제공합니다.
