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Near Memory Hardware Accelerators for Real-Time Radio Frequency Signal Computation
Near Memory Hardware Accelerators for Real-Time Radio Frequency Signal Computation
Near Memory Hardware Accelerators for Real-Time Radio Frequency Signal Computation

Detailed Information

자료유형  
 학위논문 서양
최종처리일시  
20260202105553
ISBN  
9798263399030
DDC  
741
저자명  
Mukherjee, Mandovi.
서명/저자  
Near Memory Hardware Accelerators for Real-Time Radio Frequency Signal Computation
발행사항  
[Sl] : Georgia Institute of Technology, 2023
발행사항  
Ann Arbor : ProQuest Dissertations & Theses, 2023
형태사항  
120 p
주기사항  
Source: Dissertations Abstracts International, Volume: 87-05, Section: B.
주기사항  
Advisor: Mukhopadhyay, Saibal.
학위논문주기  
Thesis (Ph.D.)--Georgia Institute of Technology, 2023.
초록/해제  
요약Computation in real-time systems such as Radar, Process Control, Advanced Driver Assistance Systems (ADAS) present challenges of handling sample by sample processing, generating output responses at low and deterministic latency and enabling dynamic reconfigurability. Radio frequency real-time systems form particularly interesting examples of this, since the frequency of incoming samples is inherently very high, computations need to be completed with very low latency and they often tend to involve very large scale system configurations with a lot of data movement. Field Programmable Gate Array (FPGA) based accelerators have been designed to process RF computations in real-time systems but they cannot simultaneously handle the high throughput ( 200MHz) and low latency (of the order of µs) in wide bandwidth system, emphasizing the need for custom accelerators.In-memory or near memory accelerators have shown promise for computation in hardware accelerators involving a large volume of data. Processing-in-Memory (PIM) has proved to be an elegant solution for accelerating Vector Matrix Multiplication (VMM), which forms the backbone of computation in traditional as well as RF Machine Learning. First, this thesis demonstrates a localized multifunctional control based processingin-memory accelerator with support for VMM with flexible precision, floating point and complex numbers. The test-chip is fabricated in 65nm CMOS and shows a measured compute efficiency, normalized to memory size, of 34 GOPS/W/KB at 177MHz. The PIM accelerator with multifunctional control can enable in-memory radio frequency machine learning and linear algebraic signal processing and may be suitable for dense computation in real-time systems, but is restricted in terms of latency.Second, the thesis proposes an ASIC based near-memory distributed control architecture for storage and distribution of real-time streaming digital RF data with simultaneous optimization of throughput and latency, specifically for sparse calculations. A small scale prototype design for the distributed control is fabricated in 28nm CMOS for application to a real-time RF emulator testbed with requirements of high throughput and deterministic, low latency. C++ based cycle level implementation of the proposed architecture, sparse Finite Impulse Response (FIR) filtering application analysis and measurement results from the test-chip in 28nm CMOS validate the proposed autonomous distributed control. Finally, the thesis considers a larger scale design of the proposed distributed control and discusses its end-to-end implementation in 28nm CMOS along with simulation results.
일반주제명  
Design
일반주제명  
Batch processing
일반주제명  
C plus plus
일반주제명  
Radio frequency
일반주제명  
Bandwidths
일반주제명  
Bypass
일반주제명  
Signal processing
일반주제명  
Field programmable gate arrays
일반주제명  
Computer science
일반주제명  
Electrical engineering
일반주제명  
Industrial engineering
기타저자  
Georgia Institute of Technology.
기본자료저록  
Dissertations Abstracts International. 87-05B.
전자적 위치 및 접속  
로그인 후 원문을 볼 수 있습니다.

MARC

 008260126s2023        us                              c    eng  d
■001000017360598
■00520260202105553
■006m          o    d                
■007cr#unu||||||||
■020    ▼a9798263399030
■035    ▼a(MiAaPQ)AAI32315833
■035    ▼a(MiAaPQ)GeorgiaTech75173
■040    ▼aMiAaPQ▼cMiAaPQ
■0820  ▼a741
■1001  ▼aMukherjee,  Mandovi.
■24510▼aNear  Memory  Hardware  Accelerators  for  Real-Time  Radio  Frequency  Signal  Computation
■260    ▼a[Sl]▼bGeorgia  Institute  of  Technology▼c2023
■260  1▼aAnn  Arbor▼bProQuest  Dissertations  &  Theses▼c2023
■300    ▼a120  p
■500    ▼aSource:  Dissertations  Abstracts  International,  Volume:  87-05,  Section:  B.
■500    ▼aAdvisor:  Mukhopadhyay,  Saibal.
■5021  ▼aThesis  (Ph.D.)--Georgia  Institute  of  Technology,  2023.
■520    ▼aComputation  in  real-time  systems  such  as  Radar,  Process  Control,  Advanced  Driver  Assistance  Systems  (ADAS)  present  challenges  of  handling  sample  by  sample  processing,  generating  output  responses  at  low  and  deterministic  latency  and  enabling  dynamic  reconfigurability.  Radio  frequency  real-time  systems  form  particularly  interesting  examples  of  this,  since  the  frequency  of  incoming  samples  is  inherently  very  high,  computations  need  to  be  completed  with  very  low  latency  and  they  often  tend  to  involve  very  large  scale  system  configurations  with  a  lot  of  data  movement.  Field  Programmable  Gate  Array  (FPGA)  based  accelerators  have  been  designed  to  process  RF  computations  in  real-time  systems  but  they  cannot  simultaneously  handle  the  high  throughput  (    200MHz)  and  low  latency  (of  the  order  of  µs)  in  wide  bandwidth  system,  emphasizing  the  need  for  custom  accelerators.In-memory  or  near  memory  accelerators  have  shown  promise  for  computation  in  hardware  accelerators  involving  a  large  volume  of  data.  Processing-in-Memory  (PIM)  has  proved  to  be  an  elegant  solution  for  accelerating  Vector  Matrix  Multiplication  (VMM),  which  forms  the  backbone  of  computation  in  traditional  as  well  as  RF  Machine  Learning.  First,  this  thesis  demonstrates  a  localized  multifunctional  control  based  processingin-memory  accelerator  with  support  for  VMM  with  flexible  precision,  floating  point  and  complex  numbers.  The  test-chip  is  fabricated  in  65nm  CMOS  and  shows  a  measured  compute  efficiency,  normalized  to  memory  size,  of  34  GOPS/W/KB  at  177MHz.  The  PIM  accelerator  with  multifunctional  control  can  enable  in-memory  radio  frequency  machine  learning  and  linear  algebraic  signal  processing  and  may  be  suitable  for  dense  computation  in  real-time  systems,  but  is  restricted  in  terms  of  latency.Second,  the  thesis  proposes  an  ASIC  based  near-memory  distributed  control  architecture  for  storage  and  distribution  of  real-time  streaming  digital  RF  data  with  simultaneous  optimization  of  throughput  and  latency,  specifically  for  sparse  calculations.  A  small  scale  prototype  design  for  the  distributed  control  is  fabricated  in  28nm  CMOS  for  application  to  a  real-time  RF  emulator  testbed  with  requirements  of  high  throughput  and  deterministic,  low  latency.  C++  based  cycle  level  implementation  of  the  proposed  architecture,  sparse  Finite  Impulse  Response  (FIR)  filtering  application  analysis  and  measurement  results  from  the  test-chip  in  28nm  CMOS  validate  the  proposed  autonomous  distributed  control.  Finally,  the  thesis  considers  a  larger  scale  design  of  the  proposed  distributed  control  and  discusses  its  end-to-end  implementation  in  28nm  CMOS  along  with  simulation  results.
■590    ▼aSchool  code:  0078.
■650  4▼aDesign
■650  4▼aBatch  processing
■650  4▼aC  plus  plus
■650  4▼aRadio  frequency
■650  4▼aBandwidths
■650  4▼aBypass
■650  4▼aSignal  processing
■650  4▼aField  programmable  gate  arrays
■650  4▼aComputer  science
■650  4▼aElectrical  engineering
■650  4▼aIndustrial  engineering
■690    ▼a0389
■690    ▼a0800
■690    ▼a0984
■690    ▼a0544
■690    ▼a0546
■71020▼aGeorgia  Institute  of  Technology.
■7730  ▼tDissertations  Abstracts  International▼g87-05B.
■790    ▼a0078
■791    ▼aPh.D.
■792    ▼a2023
■793    ▼aEnglish
■85640▼uhttp://www.riss.kr/pdu/ddodLink.do?id=T17360598▼nKERIS▼z이  자료의  원문은  한국교육학술정보원에서  제공합니다.

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