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Hybrid Baud-Rate CDR and Clock Distribution Techniques for High-Speed 100Gbps Wireline Receiver
Hybrid Baud-Rate CDR and Clock Distribution Techniques for High-Speed 100Gbps Wireline Receiver
상세정보
- 자료유형
- 학위논문 서양
- 최종처리일시
- 20260202105111
- ISBN
- 9798293893225
- DDC
- 621.3
- 저자명
- Shih, Yi-Hsuan.
- 서명/저자
- Hybrid Baud-Rate CDR and Clock Distribution Techniques for High-Speed 100Gbps Wireline Receiver
- 발행사항
- [Sl] : University of California, Berkeley, 2025
- 발행사항
- Ann Arbor : ProQuest Dissertations & Theses, 2025
- 형태사항
- 159 p
- 주기사항
- Source: Dissertations Abstracts International, Volume: 87-04, Section: B.
- 주기사항
- Advisor: Stojanovic, Vladimir;Nikolic, Borivoje.
- 학위논문주기
- Thesis (Ph.D.)--University of California, Berkeley, 2025.
- 초록/해제
- 요약With increasing demands in AI and MIMO systems, wireline link speeds have surged beyond 100Gbps, intensifying inter-symbol interference (ISI), and challenging traditional feedback- based equalization techniques like decision feedback equalizers (DFE) due to timing con- straints. To overcome feedback loop limitations, feedforward MLSE was proposed, avoiding complex feedback but still introducing significant computational complexity.This thesis presents a new hybrid clock data recovery algorithm (CDR) that leverages the complexity of the feedforward MLSE to improve the CDR locking performance and ro- bustness to channel variations. Our approach combines the Mueller-Muller algorithm with a data-level maximization algorithm, achieving baud-rate CDR locking with reduced hardware overhead and steady-state stability without additional dithering.An evaluation framework is developed to compare various CDR algorithms (Mueller-Muller, dLev maximization, and hybrid CDR) in terms of locking position and steady-state jitter by Markov chain analysis. The results indicate that hybrid CDR outperforms in locking accuracy and jitter resilience.Our hybrid CDR, implemented in 16nm technology node, includes an innovative octature generator with an injection-locked oscillator for clock distribution. Verification using a digital SystemVerilog environment improves simulation accuracy and reduces overall verification time for the receiver system.
- 일반주제명
- Electrical engineering
- 일반주제명
- Computer engineering
- 일반주제명
- Computer science
- 기타저자
- University of California, Berkeley Electrical Engineering & Computer Sciences
- 기본자료저록
- Dissertations Abstracts International. 87-04B.
- 전자적 위치 및 접속
- 로그인 후 원문을 볼 수 있습니다.
MARC
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■040 ▼aMiAaPQ▼cMiAaPQ
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■1001 ▼aShih, Yi-Hsuan.
■24510▼aHybrid Baud-Rate CDR and Clock Distribution Techniques for High-Speed 100Gbps Wireline Receiver
■260 ▼a[Sl]▼bUniversity of California, Berkeley▼c2025
■260 1▼aAnn Arbor▼bProQuest Dissertations & Theses▼c2025
■300 ▼a159 p
■500 ▼aSource: Dissertations Abstracts International, Volume: 87-04, Section: B.
■500 ▼aAdvisor: Stojanovic, Vladimir;Nikolic, Borivoje.
■5021 ▼aThesis (Ph.D.)--University of California, Berkeley, 2025.
■520 ▼aWith increasing demands in AI and MIMO systems, wireline link speeds have surged beyond 100Gbps, intensifying inter-symbol interference (ISI), and challenging traditional feedback- based equalization techniques like decision feedback equalizers (DFE) due to timing con- straints. To overcome feedback loop limitations, feedforward MLSE was proposed, avoiding complex feedback but still introducing significant computational complexity.This thesis presents a new hybrid clock data recovery algorithm (CDR) that leverages the complexity of the feedforward MLSE to improve the CDR locking performance and ro- bustness to channel variations. Our approach combines the Mueller-Muller algorithm with a data-level maximization algorithm, achieving baud-rate CDR locking with reduced hardware overhead and steady-state stability without additional dithering.An evaluation framework is developed to compare various CDR algorithms (Mueller-Muller, dLev maximization, and hybrid CDR) in terms of locking position and steady-state jitter by Markov chain analysis. The results indicate that hybrid CDR outperforms in locking accuracy and jitter resilience.Our hybrid CDR, implemented in 16nm technology node, includes an innovative octature generator with an injection-locked oscillator for clock distribution. Verification using a digital SystemVerilog environment improves simulation accuracy and reduces overall verification time for the receiver system.
■590 ▼aSchool code: 0028.
■650 4▼aElectrical engineering
■650 4▼aComputer engineering
■650 4▼aComputer science
■653 ▼aDecision feedback equalizers
■653 ▼aClock data recovery
■653 ▼aInter-symbol interference
■653 ▼aAdditional dithering
■653 ▼aOctature generator
■690 ▼a0544
■690 ▼a0464
■690 ▼a0984
■71020▼aUniversity of California, Berkeley▼bElectrical Engineering & Computer Sciences.
■7730 ▼tDissertations Abstracts International▼g87-04B.
■790 ▼a0028
■791 ▼aPh.D.
■792 ▼a2025
■793 ▼aEnglish
■85640▼uhttp://www.riss.kr/pdu/ddodLink.do?id=T17359381▼nKERIS▼z이 자료의 원문은 한국교육학술정보원에서 제공합니다.
