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Physical Side-Channel Vulnerability Assessment of Implementations of Cryptographic Algorithms
Physical Side-Channel Vulnerability Assessment of Implementations of Cryptographic Algorit...
Physical Side-Channel Vulnerability Assessment of Implementations of Cryptographic Algorithms

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자료유형  
 학위논문 서양
최종처리일시  
20260209102908
ISBN  
9798265406316
DDC  
000
저자명  
Golder, Anupam.
서명/저자  
Physical Side-Channel Vulnerability Assessment of Implementations of Cryptographic Algorithms
발행사항  
[Sl] : Georgia Institute of Technology, 2023
발행사항  
Ann Arbor : ProQuest Dissertations & Theses, 2023
형태사항  
101 p
주기사항  
Source: Dissertations Abstracts International, Volume: 87-05, Section: B.
주기사항  
Advisor: Raychowdhury, Arijit.
학위논문주기  
Thesis (Ph.D.)--Georgia Institute of Technology, 2023.
초록/해제  
요약The objective of the proposed research is to better analyze physical side-channel vulnerabilities, with a specific focus on the power and electromagnetic (EM) side channels of both software and hardware implementations of cryptographic algorithms. First, we observed that, while performing the side-channel analysis (SCA) of such implementations, the existing body of works primarily focused on proposing better neural network (NN) models to achieve higher accuracy at recovering the secret information (i.e., key or message), which is why portability (profiling and attacking different devices running the same implementation) and interpretability (how the leakages are learned) issues of the NN models were largely overlooked. We demonstrated how this portability issue manifests in the NN-based power/EM SCA on a software implementation of the current National Institute of Standards and Technology (NIST) symmetric-key encryption standard, namely advanced encryption standard (AES). We proposed an efficient cross-device attack technique using multi-device training and pre-processing of traces under practical settings. Second, we investigated the interpretability of NN models used in SCA to gain insight into which features (i.e., points or time samples) contribute the most to the classification decision by validating the relevance scores of features from the NN models using gradient-based post hoc explanation methods to the ones obtained by traditional points of interest (PoI) selection methods. Third, we performed a power side-channel vulnerability assessment of a parallel hardware implementation of one of the finalists of the NIST lightweight cryptography (LWC) competition, namely XOODYAK. We developed novel hypothetical leakage models specific to the algorithm and demonstrated successful attacks on its INITIALIZE and ABSORB phases using correlation power analysis (CPA) and NN-based profiled SCA techniques. Fourth, we demonstrated a single-trace profiled attack on a constant-time hardware implementation of a cumulative distribution table (CDT)-based discrete Gaussian (DG) sampler used in some lattice-based post-quantum cryptography (PQC) and fully homomorphic encryption (FHE)algorithms that rely on the hardness of learning with errors (LWE) problem. Finally, we also collaborated on developing generic countermeasures, such as a sensor to proactively detect an ongoing attack and signature attenuation techniques to reduce the signal-to-noise ratio (SNR) of the side-channel traces observable by an adversary to ensure implementation security against such physical side-channel attacks.
일반주제명  
Universal Serial Bus
일반주제명  
Cryptography
일반주제명  
Receivers & amplifiers
일반주제명  
Software
일반주제명  
Integrated circuits
일반주제명  
Success
일반주제명  
Fourier transforms
일반주제명  
Semiconductors
일반주제명  
Signal to noise ratio
일반주제명  
Neural networks
일반주제명  
Radio frequency identification
일반주제명  
Digital signatures
일반주제명  
Field programmable gate arrays
일반주제명  
Electrical engineering
일반주제명  
Mathematics
기타저자  
Georgia Institute of Technology.
기본자료저록  
Dissertations Abstracts International. 87-05B.
전자적 위치 및 접속  
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MARC

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■1001  ▼aGolder,  Anupam.
■24510▼aPhysical  Side-Channel  Vulnerability  Assessment  of  Implementations  of  Cryptographic  Algorithms
■260    ▼a[Sl]▼bGeorgia  Institute  of  Technology▼c2023
■260  1▼aAnn  Arbor▼bProQuest  Dissertations  &  Theses▼c2023
■300    ▼a101  p
■500    ▼aSource:  Dissertations  Abstracts  International,  Volume:  87-05,  Section:  B.
■500    ▼aAdvisor:  Raychowdhury,  Arijit.
■5021  ▼aThesis  (Ph.D.)--Georgia  Institute  of  Technology,  2023.
■520    ▼aThe  objective  of  the  proposed  research  is  to  better  analyze  physical  side-channel  vulnerabilities,  with  a  specific  focus  on  the  power  and  electromagnetic  (EM)  side  channels  of  both  software  and  hardware  implementations  of  cryptographic  algorithms.  First,  we  observed  that,  while  performing  the  side-channel  analysis  (SCA)  of  such  implementations,  the  existing  body  of  works  primarily  focused  on  proposing  better  neural  network  (NN)  models  to  achieve  higher  accuracy  at  recovering  the  secret  information  (i.e.,  key  or  message),  which  is  why  portability  (profiling  and  attacking  different  devices  running  the  same  implementation)  and  interpretability  (how  the  leakages  are  learned)  issues  of  the  NN  models  were  largely  overlooked.  We  demonstrated  how  this  portability  issue  manifests  in  the  NN-based  power/EM  SCA  on  a  software  implementation  of  the  current  National  Institute  of  Standards  and  Technology  (NIST)  symmetric-key  encryption  standard,  namely  advanced  encryption  standard  (AES).  We  proposed  an  efficient  cross-device  attack  technique  using  multi-device  training  and  pre-processing  of  traces  under  practical  settings.  Second,  we  investigated  the  interpretability  of  NN  models  used  in  SCA  to  gain  insight  into  which  features  (i.e.,  points  or  time  samples)  contribute  the  most  to  the  classification  decision  by  validating  the  relevance  scores  of  features  from  the  NN  models  using  gradient-based  post  hoc  explanation  methods  to  the  ones  obtained  by  traditional  points  of  interest  (PoI)  selection  methods.  Third,  we  performed  a  power  side-channel  vulnerability  assessment  of  a  parallel  hardware  implementation  of  one  of  the  finalists  of  the  NIST  lightweight  cryptography  (LWC)  competition,  namely  XOODYAK.  We  developed  novel  hypothetical  leakage  models  specific  to  the  algorithm  and  demonstrated  successful  attacks  on  its  INITIALIZE  and  ABSORB  phases  using  correlation  power  analysis  (CPA)  and  NN-based  profiled  SCA  techniques.  Fourth,  we  demonstrated  a  single-trace  profiled  attack  on  a  constant-time  hardware  implementation  of  a  cumulative  distribution  table  (CDT)-based  discrete  Gaussian  (DG)  sampler  used  in  some  lattice-based  post-quantum  cryptography  (PQC)  and  fully  homomorphic  encryption  (FHE)algorithms  that  rely  on  the  hardness  of  learning  with  errors  (LWE)  problem.  Finally,  we  also  collaborated  on  developing  generic  countermeasures,  such  as  a  sensor  to  proactively  detect  an  ongoing  attack  and  signature  attenuation  techniques  to  reduce  the  signal-to-noise  ratio  (SNR)  of  the  side-channel  traces  observable  by  an  adversary  to  ensure  implementation  security  against  such  physical  side-channel  attacks.
■590    ▼aSchool  code:  0078.
■650  4▼aUniversal  Serial  Bus
■650  4▼aCryptography
■650  4▼aReceivers  &  amplifiers
■650  4▼aSoftware
■650  4▼aIntegrated  circuits
■650  4▼aSuccess
■650  4▼aFourier  transforms
■650  4▼aSemiconductors
■650  4▼aSignal  to  noise  ratio
■650  4▼aNeural  networks
■650  4▼aRadio  frequency  identification
■650  4▼aDigital  signatures
■650  4▼aField  programmable  gate  arrays
■650  4▼aElectrical  engineering
■650  4▼aMathematics
■690    ▼a0800
■690    ▼a0544
■690    ▼a0405
■71020▼aGeorgia  Institute  of  Technology.
■7730  ▼tDissertations  Abstracts  International▼g87-05B.
■790    ▼a0078
■791    ▼aPh.D.
■792    ▼a2023
■793    ▼aEnglish
■85640▼uhttp://www.riss.kr/pdu/ddodLink.do?id=T17365988▼nKERIS▼z이  자료의  원문은  한국교육학술정보원에서  제공합니다.

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