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Parallel and Heterogeneous Computing for Static Timing Analysis
Parallel and Heterogeneous Computing for Static Timing Analysis
상세정보
- 자료유형
- 학위논문 서양
- 최종처리일시
- 20260209102837
- ISBN
- 9798314842607
- DDC
- 621.3
- 저자명
- Guo, Guannan.
- 서명/저자
- Parallel and Heterogeneous Computing for Static Timing Analysis
- 발행사항
- [Sl] : University of Illinois at Urbana-Champaign, 2023
- 발행사항
- Ann Arbor : ProQuest Dissertations & Theses, 2023
- 형태사항
- 97 p
- 주기사항
- Source: Dissertations Abstracts International, Volume: 86-11, Section: B.
- 주기사항
- Advisor: Wong, Martin D. F.
- 학위논문주기
- Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 2023.
- 초록/해제
- 요약The increasing complexity in digital design has spurred demand for faster design closure. As a primary timing measurement tool frequently used in design stage and optimization stage, static timing analysis (STA) has become one of the major performance bottlenecks in digital design. In this thesis, we study a novel parallel programming model and heterogeneous computing algorithms to boost timing analysis. As multi-core systems have become common in modern electronics, how to fit timing analysis into the multi-threading and heterogeneous computing environment is a trending research topic. We explore this direction with a new task-based multi-threading framework and several heterogeneous computing algorithms. We demonstrate their superior efficiency over existing tools. Critical path generation is a major objective timing analysis. Optimization tools always need to report on critical paths under several path constraints.In Chapter 1, we propose a path generation algorithm which can fulfill all practical path constraints and outperforms an industrial timing analysis tool. We also highlight its potential for multi-threading by leveraging a unified framework to task dependency graph, called Taskflow.In Chapter 2, we point out the scalability limitation by parallelizing with a multi-core CPU system. So we are highly motivated to accelerate the process of path generation in Path-based Analysis (PBA) within a heterogeneous computing environment. Our GPU-accelerated algorithm promotes PBA to a new performance milestone.In Chapter 3, we introduce an algorithm that enables path constraints satisfaction on the GPU. Our algorithm maintains high computation throughput while exploring critical paths in the search space required by the path constraints.In Chapter 4, we further improve our GPU-accelerated PBA algorithm with fine-grained optimizations. We integrate these optimizations together as a unified framework, which achieves speed-up for 3-5 times.In Chapter 5, we propose a STA graph partitioning framework that overcomes the GPU memory bottleneck. We believe this partitioning framework can allow us to offload the STA workload of industrial designs to multiple GPUs for further acceleration. The last chapter concludes this thesis and highlights the main contributions. We also point to several directions for the future work.
- 일반주제명
- Electrical engineering
- 일반주제명
- Computer engineering
- 일반주제명
- Computer science
- 키워드
- Multi-threading
- 기타저자
- University of Illinois at Urbana-Champaign Electrical & Computer Eng
- 기본자료저록
- Dissertations Abstracts International. 86-11B.
- 전자적 위치 및 접속
- 로그인 후 원문을 볼 수 있습니다.
MARC
008260203s2023 us c eng d■001000017365847
■00520260209102837
■006m o d
■007cr#unu||||||||
■020 ▼a9798314842607
■035 ▼a(MiAaPQ)AAI32063691
■035 ▼a(MiAaPQ)httphdlhandlenet2142120199
■040 ▼aMiAaPQ▼cMiAaPQ
■0820 ▼a621.3
■1001 ▼aGuo, Guannan.
■24510▼aParallel and Heterogeneous Computing for Static Timing Analysis
■260 ▼a[Sl]▼bUniversity of Illinois at Urbana-Champaign▼c2023
■260 1▼aAnn Arbor▼bProQuest Dissertations & Theses▼c2023
■300 ▼a97 p
■500 ▼aSource: Dissertations Abstracts International, Volume: 86-11, Section: B.
■500 ▼aAdvisor: Wong, Martin D. F.
■5021 ▼aThesis (Ph.D.)--University of Illinois at Urbana-Champaign, 2023.
■520 ▼aThe increasing complexity in digital design has spurred demand for faster design closure. As a primary timing measurement tool frequently used in design stage and optimization stage, static timing analysis (STA) has become one of the major performance bottlenecks in digital design. In this thesis, we study a novel parallel programming model and heterogeneous computing algorithms to boost timing analysis. As multi-core systems have become common in modern electronics, how to fit timing analysis into the multi-threading and heterogeneous computing environment is a trending research topic. We explore this direction with a new task-based multi-threading framework and several heterogeneous computing algorithms. We demonstrate their superior efficiency over existing tools. Critical path generation is a major objective timing analysis. Optimization tools always need to report on critical paths under several path constraints.In Chapter 1, we propose a path generation algorithm which can fulfill all practical path constraints and outperforms an industrial timing analysis tool. We also highlight its potential for multi-threading by leveraging a unified framework to task dependency graph, called Taskflow.In Chapter 2, we point out the scalability limitation by parallelizing with a multi-core CPU system. So we are highly motivated to accelerate the process of path generation in Path-based Analysis (PBA) within a heterogeneous computing environment. Our GPU-accelerated algorithm promotes PBA to a new performance milestone.In Chapter 3, we introduce an algorithm that enables path constraints satisfaction on the GPU. Our algorithm maintains high computation throughput while exploring critical paths in the search space required by the path constraints.In Chapter 4, we further improve our GPU-accelerated PBA algorithm with fine-grained optimizations. We integrate these optimizations together as a unified framework, which achieves speed-up for 3-5 times.In Chapter 5, we propose a STA graph partitioning framework that overcomes the GPU memory bottleneck. We believe this partitioning framework can allow us to offload the STA workload of industrial designs to multiple GPUs for further acceleration. The last chapter concludes this thesis and highlights the main contributions. We also point to several directions for the future work.
■590 ▼aSchool code: 0090.
■650 4▼aElectrical engineering
■650 4▼aComputer engineering
■650 4▼aComputer science
■653 ▼aStatic timing analysis
■653 ▼aParallel and heterogeneous computing
■653 ▼aMulti-threading
■653 ▼aPath-based Analysis
■653 ▼aGPU memory bottleneck
■690 ▼a0544
■690 ▼a0984
■690 ▼a0464
■71020▼aUniversity of Illinois at Urbana-Champaign▼bElectrical & Computer Eng.
■7730 ▼tDissertations Abstracts International▼g86-11B.
■790 ▼a0090
■791 ▼aPh.D.
■792 ▼a2023
■793 ▼aEnglish
■85640▼uhttp://www.riss.kr/pdu/ddodLink.do?id=T17365847▼nKERIS▼z이 자료의 원문은 한국교육학술정보원에서 제공합니다.
