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Design-Technology Co-Optimization of Ferroelectric Devices for Capacitive In-Memory Computing and On-Chip Buffers
Design-Technology Co-Optimization of Ferroelectric Devices for Capacitive In-Memory Computing and On-Chip Buffers
상세정보
- 자료유형
- 학위논문 서양
- 최종처리일시
- 20260202105522
- ISBN
- 9798263339173
- DDC
- 620
- 저자명
- Luo, Yuan-Chun.
- 서명/저자
- Design-Technology Co-Optimization of Ferroelectric Devices for Capacitive In-Memory Computing and On-Chip Buffers
- 발행사항
- [Sl] : Georgia Institute of Technology, 2024
- 발행사항
- Ann Arbor : ProQuest Dissertations & Theses, 2024
- 형태사항
- 145 p
- 주기사항
- Source: Dissertations Abstracts International, Volume: 87-05, Section: A.
- 주기사항
- Advisor: Yu, Shimeng.
- 학위논문주기
- Thesis (Ph.D.)--Georgia Institute of Technology, 2024.
- 초록/해제
- 요약Ferroelectric memories have been widely investigated for both analog ComputeIn-Memory (CIM) and buffer memory applications. In conventional analog CIM, weights are represented by the conductance of non-volatile resistive memories. However, these resistive memory arrays suffer from high static power, serious IR drop, and sneak-path issues. To overcome these challenges, ferroelectric "capacitive" crossbar arrays are proposed in this thesis since the capacitive approach (1) only consumes dynamic power, (2) has no DC sneak paths, (3) avoids IR drop along wires, and (4) has a high 3D stacking potential. In this thesis, ferroelectric capacitive crossbar arrays are investigated from device physics, device/array measurement, circuit simulation, to system-level benchmarking, where a cross-layer framework is built to connect the device and circuit parameters to system-level metrics. On the other hand, ferroelectric non-volatile memories as embedded storage units are also investigated. More specifically, an endurance-aware compiler is built to estimate the impact of the endurance issues of Ferroelectric Random-Access Memory (FeRAM) on system lifetime; 2T1F FeRAM is proposed for its ultra-compact cell area and low-power characteristics compared to the conventional 1T1F FeRAM; The temperature dependency of FeRAM endurance and sense margins will also be analyzed. Besides FeRAM, two other ferroelectric on-chip memories will be introduced. First, a ferroelectric non-volatile SRAM will be investigated due to its zero-leakage and instant-on advantages for edge devices with low active rates. Finally, a ferroelectric tunnel junction with high on/off ratios and multiple memory states per cell will be demonstrated.
- 일반주제명
- Silicon
- 일반주제명
- Physics
- 일반주제명
- Investigations
- 일반주제명
- Wire
- 일반주제명
- Synapses
- 일반주제명
- Neural networks
- 일반주제명
- Design
- 일반주제명
- Energy efficiency
- 일반주제명
- Transistors
- 일반주제명
- Energy consumption
- 일반주제명
- Electrical engineering
- 일반주제명
- Sustainability
- 기본자료저록
- Dissertations Abstracts International. 87-05A.
- 전자적 위치 및 접속
- 로그인 후 원문을 볼 수 있습니다.
MARC
008260126s2024 us c eng d■001000017360420
■00520260202105522
■006m o d
■007cr#unu||||||||
■020 ▼a9798263339173
■035 ▼a(MiAaPQ)AAI32309626
■035 ▼a(MiAaPQ)GeorgiaTech77708
■040 ▼aMiAaPQ▼cMiAaPQ
■0820 ▼a620
■1001 ▼aLuo, Yuan-Chun.
■24510▼aDesign-Technology Co-Optimization of Ferroelectric Devices for Capacitive In-Memory Computing and On-Chip Buffers
■260 ▼a[Sl]▼bGeorgia Institute of Technology▼c2024
■260 1▼aAnn Arbor▼bProQuest Dissertations & Theses▼c2024
■300 ▼a145 p
■500 ▼aSource: Dissertations Abstracts International, Volume: 87-05, Section: A.
■500 ▼aAdvisor: Yu, Shimeng.
■5021 ▼aThesis (Ph.D.)--Georgia Institute of Technology, 2024.
■520 ▼aFerroelectric memories have been widely investigated for both analog ComputeIn-Memory (CIM) and buffer memory applications. In conventional analog CIM, weights are represented by the conductance of non-volatile resistive memories. However, these resistive memory arrays suffer from high static power, serious IR drop, and sneak-path issues. To overcome these challenges, ferroelectric "capacitive" crossbar arrays are proposed in this thesis since the capacitive approach (1) only consumes dynamic power, (2) has no DC sneak paths, (3) avoids IR drop along wires, and (4) has a high 3D stacking potential. In this thesis, ferroelectric capacitive crossbar arrays are investigated from device physics, device/array measurement, circuit simulation, to system-level benchmarking, where a cross-layer framework is built to connect the device and circuit parameters to system-level metrics. On the other hand, ferroelectric non-volatile memories as embedded storage units are also investigated. More specifically, an endurance-aware compiler is built to estimate the impact of the endurance issues of Ferroelectric Random-Access Memory (FeRAM) on system lifetime; 2T1F FeRAM is proposed for its ultra-compact cell area and low-power characteristics compared to the conventional 1T1F FeRAM; The temperature dependency of FeRAM endurance and sense margins will also be analyzed. Besides FeRAM, two other ferroelectric on-chip memories will be introduced. First, a ferroelectric non-volatile SRAM will be investigated due to its zero-leakage and instant-on advantages for edge devices with low active rates. Finally, a ferroelectric tunnel junction with high on/off ratios and multiple memory states per cell will be demonstrated.
■590 ▼aSchool code: 0078.
■650 4▼aSilicon
■650 4▼aPhysics
■650 4▼aInvestigations
■650 4▼aWire
■650 4▼aSynapses
■650 4▼aNeural networks
■650 4▼aDesign
■650 4▼aEnergy efficiency
■650 4▼aTransistors
■650 4▼aEnergy consumption
■650 4▼aElectrical engineering
■650 4▼aSustainability
■690 ▼a0389
■690 ▼a0605
■690 ▼a0800
■690 ▼a0544
■690 ▼a0640
■71020▼aGeorgia Institute of Technology.
■7730 ▼tDissertations Abstracts International▼g87-05A.
■790 ▼a0078
■791 ▼aPh.D.
■792 ▼a2024
■793 ▼aEnglish
■85640▼uhttp://www.riss.kr/pdu/ddodLink.do?id=T17360420▼nKERIS▼z이 자료의 원문은 한국교육학술정보원에서 제공합니다.
