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Signal-Chain Optimized Analog-To-Digital Converter Design
Signal-Chain Optimized Analog-To-Digital Converter Design
Signal-Chain Optimized Analog-To-Digital Converter Design

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자료유형  
 학위논문 서양
최종처리일시  
20260202105527
ISBN  
9798263351175
DDC  
620
저자명  
Xie, Tian.
서명/저자  
Signal-Chain Optimized Analog-To-Digital Converter Design
발행사항  
[Sl] : Georgia Institute of Technology, 2025
발행사항  
Ann Arbor : ProQuest Dissertations & Theses, 2025
형태사항  
114 p
주기사항  
Source: Dissertations Abstracts International, Volume: 87-05, Section: B.
주기사항  
Advisor: Li, Shaolan.
학위논문주기  
Thesis (Ph.D.)--Georgia Institute of Technology, 2025.
초록/해제  
요약Analog-to-Digital Converters (ADCs) are essential components in modern electronics. With the rapid evolution of wireless communication and wearable biomedical devices, there is a growing demand for ADCs that provide higher resolution and wider bandwidth at lower power consumption. Although various innovative architectures have been proposed to meet these requirements, most efforts have primarily focused on optimizing the ADC core while overlooking system-level components such as input driving buffers and anti-aliasing filters. These components often become the bottleneck that limits the overall performance of the system.This thesis begins by exploring ADC design challenges through a review of ADC fundamentals and conventional signal chain architectures. It then introduces three novel architectures and all of them are validated through measurements on silicon prototypes:The first work proposes a noise-mitigated Buffer-In-Loop (BIL) architecture to relax the input driving requirements and resolve the noise penalty issue. Additionally, a "nested" Error Feedback (EF)-cascaded Resonator Feed Forward (CRFF) architecture with floating inverter amplifier (FIA) is proposed for optimizing the Noise Transfer Function (NTF) with PVT robustness.The second work advances this concept by proposing an Amplifier-Reused In-Loop Buffering (AILB) architecture. This architecture intrinsically suppresses sampling kT/C noise and loop filter noise through amplifier reuse, improving the power efficiency. A prediction-and-skip algorithm is developed and implemented to prevent the amplifier from clipping and reduce the SAR conversion time. A third-order AILB compatible EF-CIFF NS and NTF leakage reshaping are also proposed to achieve a PVT robust NS with open-loop amplifier.The third work focuses on optimizing the current-sensing signal chain. An integratorbased I-V converter provides low input impedance, low noise, and low power consumption. Then, a Triple-Slope ADC is developed with second-order noise shaping, achieving large dynamic range and making it suitable for low-power biomedical applications.The contribution of this research lies in the development of signal-chain optimized ADC architectures that improve input driving capabilities, minimize power consumption, and simplify system complexity. By enabling ADCs to serve as direct sensor readouts, these innovations create a new method to build more efficient and effective electronic systems.
일반주제명  
Circuits
일반주제명  
Wireless communications
일반주제명  
Design
일반주제명  
Energy efficiency
일반주제명  
Control algorithms
일반주제명  
Spectrum allocation
일반주제명  
Bandwidths
일반주제명  
Conversion
일반주제명  
Signal processing
일반주제명  
Electrocardiography
일반주제명  
Electrical engineering
일반주제명  
Medicine
일반주제명  
Optics
일반주제명  
Sustainability
일반주제명  
Electromagnetics
기타저자  
Georgia Institute of Technology.
기본자료저록  
Dissertations Abstracts International. 87-05B.
전자적 위치 및 접속  
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MARC

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■1001  ▼aXie,  Tian.
■24510▼aSignal-Chain  Optimized  Analog-To-Digital  Converter  Design
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■260  1▼aAnn  Arbor▼bProQuest  Dissertations  &  Theses▼c2025
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■500    ▼aSource:  Dissertations  Abstracts  International,  Volume:  87-05,  Section:  B.
■500    ▼aAdvisor:  Li,  Shaolan.
■5021  ▼aThesis  (Ph.D.)--Georgia  Institute  of  Technology,  2025.
■520    ▼aAnalog-to-Digital  Converters  (ADCs)  are  essential  components  in  modern  electronics.  With  the  rapid  evolution  of  wireless  communication  and  wearable  biomedical  devices,  there  is  a  growing  demand  for  ADCs  that  provide  higher  resolution  and  wider  bandwidth  at  lower  power  consumption.  Although  various  innovative  architectures  have  been  proposed  to  meet  these  requirements,  most  efforts  have  primarily  focused  on  optimizing  the  ADC  core  while  overlooking  system-level  components  such  as  input  driving  buffers  and  anti-aliasing  filters.  These  components  often  become  the  bottleneck  that  limits  the  overall  performance  of  the  system.This  thesis  begins  by  exploring  ADC  design  challenges  through  a  review  of  ADC  fundamentals  and  conventional  signal  chain  architectures.  It  then  introduces  three  novel  architectures  and  all  of  them  are  validated  through  measurements  on  silicon  prototypes:The  first  work  proposes  a  noise-mitigated  Buffer-In-Loop  (BIL)  architecture  to  relax  the  input  driving  requirements  and  resolve  the  noise  penalty  issue.  Additionally,  a  "nested"  Error  Feedback  (EF)-cascaded  Resonator  Feed  Forward  (CRFF)  architecture  with  floating  inverter  amplifier  (FIA)  is  proposed  for  optimizing  the  Noise  Transfer  Function  (NTF)  with  PVT  robustness.The  second  work  advances  this  concept  by  proposing  an  Amplifier-Reused  In-Loop  Buffering  (AILB)  architecture.  This  architecture  intrinsically  suppresses  sampling  kT/C  noise  and  loop  filter  noise  through  amplifier  reuse,  improving  the  power  efficiency.  A  prediction-and-skip  algorithm  is  developed  and  implemented  to  prevent  the  amplifier  from  clipping  and  reduce  the  SAR  conversion  time.  A  third-order  AILB  compatible  EF-CIFF  NS  and  NTF  leakage  reshaping  are  also  proposed  to  achieve  a  PVT  robust  NS  with  open-loop  amplifier.The  third  work  focuses  on  optimizing  the  current-sensing  signal  chain.  An  integratorbased  I-V  converter  provides  low  input  impedance,  low  noise,  and  low  power  consumption.  Then,  a  Triple-Slope  ADC  is  developed  with  second-order  noise  shaping,  achieving  large  dynamic  range  and  making  it  suitable  for  low-power  biomedical  applications.The  contribution  of  this  research  lies  in  the  development  of  signal-chain  optimized  ADC  architectures  that  improve  input  driving  capabilities,  minimize  power  consumption,  and  simplify  system  complexity.  By  enabling  ADCs  to  serve  as  direct  sensor  readouts,  these  innovations  create  a  new  method  to  build  more  efficient  and  effective  electronic  systems.
■590    ▼aSchool  code:  0078.
■650  4▼aCircuits
■650  4▼aWireless  communications
■650  4▼aDesign
■650  4▼aEnergy  efficiency
■650  4▼aControl  algorithms
■650  4▼aSpectrum  allocation
■650  4▼aBandwidths
■650  4▼aConversion
■650  4▼aSignal  processing
■650  4▼aElectrocardiography
■650  4▼aElectrical  engineering
■650  4▼aMedicine
■650  4▼aOptics
■650  4▼aSustainability
■650  4▼aElectromagnetics
■690    ▼a0389
■690    ▼a0544
■690    ▼a0564
■690    ▼a0752
■690    ▼a0640
■690    ▼a0607
■71020▼aGeorgia  Institute  of  Technology.
■7730  ▼tDissertations  Abstracts  International▼g87-05B.
■790    ▼a0078
■791    ▼aPh.D.
■792    ▼a2025
■793    ▼aEnglish
■85640▼uhttp://www.riss.kr/pdu/ddodLink.do?id=T17360443▼nKERIS▼z이  자료의  원문은  한국교육학술정보원에서  제공합니다.

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