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Reliable Processing-in-Memory
Reliable Processing-in-Memory
상세정보
- 자료유형
- 학위논문 서양
- 최종처리일시
- 20260311091520.5
- ISBN
- 9798270233266
- DDC
- 620.0045
- 저자명
- Jung, Jeageun
- 서명/저자
- Reliable Processing-in-Memory / Jeageun Jung
- 발행사항
- [Sl] : The University of Texas at Austin, 2025
- 형태사항
- 1 electronic resource (150 pages)
- 주기사항
- Source: Dissertations Abstracts International, Volume: 87-06, Section: B.
- 주기사항
- Advisors: Erez, Mattan Committee members: Gerstlauer, Andreas; Swartzlander, Earl; Gurumurthi, Sudhanva; Orshansky, Michael.
- 학위논문주기
- - Ph.D. : The University of Texas at Austin, 2025.
- 초록/해제
- 요약Processing-in-memory (PIM) architectures integrate compute units within memory, enhancing performance and efficiency but introducing significant reliability challenges. These challenges arise from the inherent conflict between localized data accesses, which minimize data movement, and the necessity for non-local accesses to manage error-checking and correcting (ECC) metadata. I introduce a novel DRAM physical fault model based on empirical data and an ECC scheme specifically designed for PIM. I develop a predictive model based on a public dataset of DRAM errors which provides predictions based on a mapping to physical components in any DRAM, instead of relying on retrospective data that is only valid for already-deployed (older) DRAM technology. I also propose an ECC scheme that targets the read-dominant access patterns of near memory processing and addresses DRAM errors reported in DRAM error field studies. Furthermore, I explore reliable bank-level PIM architectures for irregular access patterns to support more applications. I demonstrate my approach in a simulated system that uses the physical fault model and a DDR5-PIM with several ECC schemes. I show that my mechanisms can minimize performance overhead while enhancing reliability.
- 언어주기
- English
- 일반주제명
- Computer science
- 일반주제명
- Information technology
- 일반주제명
- Information science
- 기타저자
- The University of Texas at Austin Electrical and Computer Engineering
- 기본자료저록
- Dissertations Abstracts International. 87-06B.
- 전자적 위치 및 접속
- 로그인 후 원문을 볼 수 있습니다.
MARC
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■00520260311091520.5
■006m o d
■007cr|nu||||||||
■020 ▼a9798270233266
■040 ▼aMiAaPQD▼beng▼cMiAaPQD▼erda
■082 ▼a620.0045
■1001 ▼aJung, Jeageun▼eauthor.
■24510▼aReliable Processing-in-Memory ▼cJeageun Jung
■260 ▼a[Sl]▼bThe University of Texas at Austin▼c2025
■264 1▼aAnn Arbor▼bProQuest Dissertations & Theses▼c2025
■300 ▼a1 electronic resource (150 pages)
■336 ▼atext▼btxt▼2rdacontent
■337 ▼acomputer▼bc▼2rdamedia
■338 ▼aonline resource▼bcr▼2rdacarrier
■500 ▼aSource: Dissertations Abstracts International, Volume: 87-06, Section: B.
■500 ▼aAdvisors: Erez, Mattan Committee members: Gerstlauer, Andreas; Swartzlander, Earl; Gurumurthi, Sudhanva; Orshansky, Michael.
■5021 ▼bPh.D.▼cThe University of Texas at Austin▼d2025.
■520 ▼aProcessing-in-memory (PIM) architectures integrate compute units within memory, enhancing performance and efficiency but introducing significant reliability challenges. These challenges arise from the inherent conflict between localized data accesses, which minimize data movement, and the necessity for non-local accesses to manage error-checking and correcting (ECC) metadata. I introduce a novel DRAM physical fault model based on empirical data and an ECC scheme specifically designed for PIM. I develop a predictive model based on a public dataset of DRAM errors which provides predictions based on a mapping to physical components in any DRAM, instead of relying on retrospective data that is only valid for already-deployed (older) DRAM technology. I also propose an ECC scheme that targets the read-dominant access patterns of near memory processing and addresses DRAM errors reported in DRAM error field studies. Furthermore, I explore reliable bank-level PIM architectures for irregular access patterns to support more applications. I demonstrate my approach in a simulated system that uses the physical fault model and a DDR5-PIM with several ECC schemes. I show that my mechanisms can minimize performance overhead while enhancing reliability.
■546 ▼aEnglish
■590 ▼aSchool code: 0227
■650 4▼aComputer science
■650 4▼aInformation technology
■650 4▼aInformation science
■653 ▼aProcessing-in-memory
■653 ▼aError-checking and correcting
■653 ▼aError field studies
■653 ▼aPhysical fault model
■7102 ▼aThe University of Texas at Austin▼bElectrical and Computer Engineering.▼edegree granting institution.
■7201 ▼aErez, Mattan▼edegree supervisor.
■7730 ▼tDissertations Abstracts International▼g87-06B.
■85640▼uhttp://www.riss.kr/pdu/ddodLink.do?id=T17361257▼nKERIS▼z이 자료의 원문은 한국교육학술정보원에서 제공합니다.
