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Cryogenic CMOS Circuits for High Performance Digital Systems
Cryogenic CMOS Circuits for High Performance Digital Systems
상세정보
- 자료유형
- 학위논문 서양
- 최종처리일시
- 20260202105505
- ISBN
- 9798263326319
- DDC
- 620
- 서명/저자
- Cryogenic CMOS Circuits for High Performance Digital Systems
- 발행사항
- [Sl] : Georgia Institute of Technology, 2024
- 발행사항
- Ann Arbor : ProQuest Dissertations & Theses, 2024
- 형태사항
- 169 p
- 주기사항
- Source: Dissertations Abstracts International, Volume: 87-05, Section: B.
- 주기사항
- Advisor: Raychowdhury, Arijit.
- 학위논문주기
- Thesis (Ph.D.)--Georgia Institute of Technology, 2024.
- 초록/해제
- 요약There has been an ever increasing demand for energy efficient processors, more recently so with the emergence of Artificial Intelligence, Machine Learning and Large Language Models. Cryogenic computing is a transformative technology that uses ultra low temperatures (-196◦C / 77K) to achieve higher performance and/or better energy efficiency. The superior device characteristics like higher device drive current, lower subthreshold slope, ultra low subthreshold leakage, lower interconnect resistance etc., opens multitude of design opportunities both at circuits and system level. It also enables memory technologies which are otherwise lost due to technological evolution. In this work, we show how the better device and interconnect properties translate to faster, smaller and lower power systems.To do so, we build in-house cryogenic device models well calibrated to experimentally measured data for both transistors (chapter 3) and wires (chapter 4). We use circuit concepts to intricately measure and calibrate the interconnect resistance based on a standard foundry process chip tapeout in 22nm FDSOI. The models are robust, scalable, based on industry standard platforms and aid in cryogenic circuit simulation to design higher order systems. We characterize a matrix multiplication accelerator test chip (chapter 5) across temperature built in 40nm CMOS process and demonstrate an energy efficiency improvement of up to 26%. We propose new biasing techniques for dynamic logic circuits which when benchmarked on a 64-bit domino logic adder proves to consume 41% lesser energy than the room temperature counterpart. We also co-optimize the design of 6T SRAM with technology to allow for supply voltage scaling in the presence of variation while providing 5.4x lower energy and 1.2x lower delay. We further demonstrate a 28nm hybrid 2T gain cell embedded DRAM test chip capable of operating from 4K to 300K. The memory macro shows 1.7x energy higher energy efficiency, more than 106x higher retention time and lower refresh rate at low temperature (chapter 6). Finally, we present a design technology co-optimized benchmarking of a 64-bit Arm processor. More than 12 different standard cell libraries are recharacterized at multiple temperatures and supply voltages to execute full fledged auto-place and route runs. The designs are then analyzed for power, performance and area, results of which show more than 4x improvement in energy efficiency at low temperature. We also benchmark the thermal behavior of the system and show that cryogenic computing can theoretically allow higher number of chips to be packaged together at a given thermal design power limit. Lastly, the cooling cost is analyzed and key roadblocks are identified with possible future works.
- 일반주제명
- Circuits
- 일반주제명
- High performance systems
- 일반주제명
- Energy consumption
- 일반주제명
- Computer science
- 일반주제명
- Electrical engineering
- 기본자료저록
- Dissertations Abstracts International. 87-05B.
- 전자적 위치 및 접속
- 로그인 후 원문을 볼 수 있습니다.
MARC
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■00520260202105505
■006m o d
■007cr#unu||||||||
■020 ▼a9798263326319
■035 ▼a(MiAaPQ)AAI32308006
■035 ▼a(MiAaPQ)GeorgiaTech78571
■040 ▼aMiAaPQ▼cMiAaPQ
■0820 ▼a620
■1001 ▼aSaligram, Rakshith.
■24510▼aCryogenic CMOS Circuits for High Performance Digital Systems
■260 ▼a[Sl]▼bGeorgia Institute of Technology▼c2024
■260 1▼aAnn Arbor▼bProQuest Dissertations & Theses▼c2024
■300 ▼a169 p
■500 ▼aSource: Dissertations Abstracts International, Volume: 87-05, Section: B.
■500 ▼aAdvisor: Raychowdhury, Arijit.
■5021 ▼aThesis (Ph.D.)--Georgia Institute of Technology, 2024.
■520 ▼aThere has been an ever increasing demand for energy efficient processors, more recently so with the emergence of Artificial Intelligence, Machine Learning and Large Language Models. Cryogenic computing is a transformative technology that uses ultra low temperatures (-196◦C / 77K) to achieve higher performance and/or better energy efficiency. The superior device characteristics like higher device drive current, lower subthreshold slope, ultra low subthreshold leakage, lower interconnect resistance etc., opens multitude of design opportunities both at circuits and system level. It also enables memory technologies which are otherwise lost due to technological evolution. In this work, we show how the better device and interconnect properties translate to faster, smaller and lower power systems.To do so, we build in-house cryogenic device models well calibrated to experimentally measured data for both transistors (chapter 3) and wires (chapter 4). We use circuit concepts to intricately measure and calibrate the interconnect resistance based on a standard foundry process chip tapeout in 22nm FDSOI. The models are robust, scalable, based on industry standard platforms and aid in cryogenic circuit simulation to design higher order systems. We characterize a matrix multiplication accelerator test chip (chapter 5) across temperature built in 40nm CMOS process and demonstrate an energy efficiency improvement of up to 26%. We propose new biasing techniques for dynamic logic circuits which when benchmarked on a 64-bit domino logic adder proves to consume 41% lesser energy than the room temperature counterpart. We also co-optimize the design of 6T SRAM with technology to allow for supply voltage scaling in the presence of variation while providing 5.4x lower energy and 1.2x lower delay. We further demonstrate a 28nm hybrid 2T gain cell embedded DRAM test chip capable of operating from 4K to 300K. The memory macro shows 1.7x energy higher energy efficiency, more than 106x higher retention time and lower refresh rate at low temperature (chapter 6). Finally, we present a design technology co-optimized benchmarking of a 64-bit Arm processor. More than 12 different standard cell libraries are recharacterized at multiple temperatures and supply voltages to execute full fledged auto-place and route runs. The designs are then analyzed for power, performance and area, results of which show more than 4x improvement in energy efficiency at low temperature. We also benchmark the thermal behavior of the system and show that cryogenic computing can theoretically allow higher number of chips to be packaged together at a given thermal design power limit. Lastly, the cooling cost is analyzed and key roadblocks are identified with possible future works.
■590 ▼aSchool code: 0078.
■650 4▼aCircuits
■650 4▼aHigh performance systems
■650 4▼aEnergy consumption
■650 4▼aHigh performance computing
■650 4▼aComputer science
■650 4▼aElectrical engineering
■690 ▼a0984
■690 ▼a0544
■71020▼aGeorgia Institute of Technology.
■7730 ▼tDissertations Abstracts International▼g87-05B.
■790 ▼a0078
■791 ▼aPh.D.
■792 ▼a2024
■793 ▼aEnglish
■85640▼uhttp://www.riss.kr/pdu/ddodLink.do?id=T17360311▼nKERIS▼z이 자료의 원문은 한국교육학술정보원에서 제공합니다.
