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1
Enabling SoC Verification Through Instruction-Level Hardware Models- [electronic resource]
Enabling SoC Verification Through Instruction-Level Hardware Models- [electronic resource]
Xing, Yue.Electrical and Computer Engineering. | Princeton University. | 2023
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2
Enabling SoC Verification Through Instruction-Level Hardware Models- [electronic resource]
Enabling SoC Verification Through Instruction-Level Hardware Models- [electronic resource]
Xing, Yue.Electrical and Computer Engineering. | Princeton University. | 2023
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3
Enabling SoC Verification Through Instruction-Level Hardware Models- [electronic resource]
Enabling SoC Verification Through Instruction-Level Hardware Models- [electronic resource]
Xing, Yue.Electrical and Computer Engineering. | Princeton University. | 2023
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4
Hybrid-Neural Synthesis of Machine Checkable Software Correctness Proofs
Hybrid-Neural Synthesis of Machine Checkable Software Correctness Proofs
Sanchez-Stern, Alex. | University of California, San Diego | 2021
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5
A Secure and Formally Verified Commodity Multiprocessor Hypervisor
A Secure and Formally Verified Commodity Multiprocessor Hypervisor
Li, Shih-Wei. | Columbia University | 2021
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6
The Hardware-Software Interface for Systems-on-Chip: Formal Modeling and Modular Verification
The Hardware-Software Interface for Systems-on-Chip: Formal Modeling and Modular Verification
Zhang, Hongce. | Princeton University | 2021
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