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MORE| No | 제목 / 내용 |
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| 1 |
INTERFACE CIRCUIT, METHOD AND DEVICE FOR STATE SWITCHING / XIAOMI INC The disclosure relates to an interface circuit, method and device for state switching and belongs to the terminal technology field. The interface circuit includes a Power Management Integrated Circuit PMIC (210), a Universal Serial Bus USB controller (220), an Integrated Circuit IC (230) and a USB interface (240), wherein ID1 of the PMIC (210) is connected with ID2 of the IC (230), and CC1 of the IC (230) is connected with CC2 in the USB interface (240); a data pin in the USB controller is connected with a data pin in the USB interface (240) through the IC (230); under a master-slave switching state, the IC (230) disconnects ID2 with CC1, and sets ID2 to high level and CC1 to low level; under a slave-master switching state, the IC (230) disconnects ID2 with CC1, and sets ID2 to low level and CC1 to high level; under a non-switching state, the IC (230) is in a state that ID2 is connected with CC1. |
| 2 |
INTERFACE CIRCUIT, AND STATE SWITCHING METHOD AND DEVICE / XIAOMI INC The present invention relates to the technical field of terminals, and in particular, to an interface circuit, and a state switching method and device. The interface circuit comprises: a power management integrated circuit (PMIC) (210), a universal serial bus (USB) controller (220), an integrated circuit (IC) (230), and a USB interface (240). A pin ID1 of the PMIC (210) and a pin ID2 of the IC (230) are mutually connected. A pin CC1 of the IC (230) and a pin CC2 of the USB interface (240) are mutually connected. A data pin of the USB controller (220) and a data pin of the USB interface (240) are mutually connected. In a master-to-slave switching state, the pin ID2 and the pin CC1 of IC (230) are disconnected, and the pin ID2 is set to be a high voltage level, and the pin CC1 is set to be a low voltage level. In a slave-to-master switching state, the pin ID2 and the pin CC1 of IC (230) are disconnected, and the pin ID2 is set to be the low voltage level, and the pin CC1 is set to be the high voltage level. In a non-switching state, the pin ID2 and the pin CC1 of IC (230) are connected. |
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ENCODER, DECODER, ENCODING METHOD, AND DECODING METHOD / PANASONIC CORPORATION There is provided an encoder that provides a termination sequence with a simple structure for LDPC-CC encoding and reduces an amount of the termination sequence transmitted to a transmission line. The LDPC-CC encoder (200) connects a first encoder (230) to a second encoder (240) to perform encoding and thereby carry out LDPC-CC encoding, the first encoder (230) performing encoding based on an partial parity check matrix for information bits (110) obtained by extracting a sequence corresponding to the information bits in a parity check matrix (100) and the second encoder (240) performing encoding based on a partial parity check matrix for parity bits (120) obtained by extracting a sequence corresponding to the parity bits in the parity check matrix (100). A termination sequence generator (210) generates a termination sequence including the same number of bits as the memory length of the first encoder (230) and provides the generated termination sequence as an input sequence. |
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Encoder, decoder, encoding method, and decoding method / Panasonic Corporation There is provided an encoder that provides a termination sequence with a simple structure for LDPC-CC encoding and reduces an amount of the termination sequence transmitted to a transmission line. The LDPC-CC encoder (200) connects a first encoder (230) to a second encoder (240) to perform encoding and thereby carry out LDPC-CC encoding, the first encoder (230) performing encoding based on an partial parity check matrix for information bits (110) obtained by extracting a sequence corresponding to the information bits in a parity check matrix (100) and the second encoder (240) performing encoding based on a partial parity check matrix for parity bits (120) obtained by extracting a sequence corresponding to the parity bits in the parity check matrix (100). A termination sequence generator (210) generates a termination sequence including the same number of bits as the memory length of the first encoder (230) and provides the generated termination sequence as an input sequence. |
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ENCODER, DECODER, ENCODING METHOD, AND DECODING METHOD / ORIHASHI, MASAYUKI There is provided an encoder that provides a termination sequence with a simple structure for LDPC-CC encoding and reduces an amount of the termination sequence transmitted to a transmission line. The LDPC-CC encoder (200) connects a first encoder (230) to a second encoder (240) to perform encoding and thereby carry out LDPC-CC encoding, the first encoder (230) performing encoding based on an information partial test matrix (110) obtained by extracting a sequence corresponding to the information bits in a test matrix (100) and the second encoder (240) performing encoding based on a parity partial test matrix (120) obtained by extracting a sequence corresponding to the parity bits in the test matrix (100). A termination sequence generator (210) generates a termination sequence including the same number of bits as the memory length of the first encoder (230) and provides the generated termination sequence as an input sequence. |
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ENCODER, DECODER, ENCODING METHOD, AND DECODING METHOD / PANASONIC CORP PROBLEM TO BE SOLVED: To provide a termination sequence for LDPC-CC encoding by a simple structure and to reduce the amount of the termination sequence to be transmitted to a transmission line. SOLUTION: An LDPC-CC encoder 200 connects a first encoder 230 to a second encoder 240 to perform encoding and thereby carry out LDPC-CC encoding, the first encoder 230 performing encoding based on an information partial text matrix 110 obtained by extracting a sequence corresponding to information bits in a text matrix 100 and the second encoder 240 performing encoding based on a parity partial text matrix 120 obtained by extracting a sequence corresponding to parity bits in the test matrix 100. A termination sequence generation unit 210 generates a termination sequence composed of the same number of bits as the memory length of the first encoder 230 and provides the generated termination sequence as an input sequence. |
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ENCODER, TRANSMISSION DEVICE AND ENCODING METHOD / PANASONIC CORP PROBLEM TO BE SOLVED: To provide a termination sequence for LDPC-CC encoding by a simple structure and to reduce the amount of the termination sequence to be transmitted to a transmission line.SOLUTION: An LDPC-CC encoder 200 connects a first encoder 230 to a second encoder 240 to perform encoding and thereby carry out LDPC-CC encoding, the first encoder 230 performing encoding based on an information partial test matrix 110 obtained by extracting a sequence corresponding to information bits in a test matrix 100 and the second encoder 240 performing encoding based on a parity partial test matrix 120 obtained by extracting a sequence corresponding to parity bits in the test matrix 100. A termination sequence generation unit 210 generates a termination sequence composed of the same number of bits as the memory length of the first encoder 230 and provides the generated termination sequence as an input sequence. |
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ENCODER, DECODER, ENCODING METHOD, AND DECODING METHOD / PANASONIC CORP PROBLEM TO BE SOLVED: To provide a termination sequence for LDPC-CC encoding by simple structure and to reduce an amount of the termination sequence to be transmitted to a transmission line.SOLUTION: An LDPC-CC encoder 200 connects a first encoder 230 to a second encoder 240 to perform encoding and thereby carry out LDPC-CC encoding. The first encoder 230 performs the encoding on the basis of an information partial text matrix 110 obtained by extracting a sequence corresponding to information bits in a text matrix 100 and the second encoder 240 performs the encoding on the basis of a parity partial text matrix 120 obtained by extracting a sequence corresponding to parity bits in the test matrix 100. A termination sequence generation unit 210 generates a termination sequence composed of the same number of bits as memory length of the first encoder 230 and provides the generated termination sequence as an input sequence. |
| 9 |
건식집어제의 제조방법 및 이에 따라 제조된 건식집어제와건식집어제 고정구 / 함문탁 본 발명은 건식 집어제에 관한 것으로 보다 상세하게는 원통형상으로 제조하여 수중에서 서서히 녹도록 하여 어류를 유인할 수 있도록 하기 위한 것으로 어분 100cc에 대하여 멸분 40 내지 60cc와 새우분말 40 내지 60cc에 물 50 내지 70cc를 혼합하여 1시간 숙성하는 1단계와 1단계에서 숙성된 혼합물에 황토 230 내지 270cc와 멸분 170 내지 220 cc를 혼합하는 2단계와 2단계에서 혼합된 혼합물을 틀에 넣고 압력을 가해 원통형상의 집어제를 제조하는 3단계와 3단계에서 제조된 집어제를 건조시키는 4단계를 포함하여 구성되는 것을 특징으로 하는 건식 집어제의 제조방법과 상기 제조방법에 의해 만들어진 건식 집어제 그리고 상기 건식 집어제를 낚시줄에 고정하기 위한 고정구를 제공하여 집어효율을 높일 수 있게 된다. |
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디스플레이 기판 및 디스플레이 패널 / 보에 테크놀로지 그룹 컴퍼니 리미티드 디스플레이 기판 및 디스플레이 패널. 해당 디스플레이 기판(01)은: 베이스 기판(10)에 설치된 복수개의 서브 픽셀(12)을 포함하며; 복수개의 서브 픽셀(12)의 각각은 발광 소자(121)와 상기 발광 소자를 구동하여 발광하는 픽셀 회로(120)를 포함하며, 픽셀 회로(120)는 구동 서브 회로(200), 데이터 입력 서브 회로(230), 임계 보상 서브 회로(240), 누전 방지 서브 회로(270) 및 저장 서브 회로(280)를 포함하며; 저장 서브 회로(280)는 저장 커패시터(Cst1)를 포함하며, 상기 저장 커패시터는 제1 전극판(CC1), 제2 전극판(CC2)과 제3 전극판(CC3)을 포함하며, 제1 전극판(CC1)과 제3 전극판(CC3)은 서로 전기적으로 연결되고 또한 상기 베이스 기판에 대해 상이한 층에 위치하며, 제2 전극판(CC2)은 베이스 기판에 수직되는 방향 상에서 각각 제1 전극판 및 상기 제3 전극판과 적어도 부분적으로 중첩된다. 해당 디스플레이 기판은 점유 공간을 증가시키지 않고도 저장 커패시터의 크기를 늘릴 수 있다. |
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MOREScienceON '보고서' 검색
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